<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29058">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amdfam10: Convert to `board_reset()`<br><br>And here comes the mess...<br><br>This just renames do_hard_reset() to do_board_reset() and keeps current<br>behaviour. As these are never called from chipset or board code but only<br>from common code, it's likely that their implementations are untested<br>and not what we actually want. Also note, that sometimes implementations<br>for rom- and ramstage differ considerably.<br><br>Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/mainboard/asus/kcma-d8/Kconfig<br>M src/mainboard/asus/kfsn4-dre/Kconfig<br>M src/mainboard/asus/kgpe-d16/Kconfig<br>M src/southbridge/amd/amd8111/Kconfig<br>M src/southbridge/amd/amd8111/early_ctrl.c<br>M src/southbridge/amd/amd8111/reset.c<br>M src/southbridge/amd/sb700/Kconfig<br>M src/southbridge/amd/sb700/reset.c<br>M src/southbridge/amd/sb800/Kconfig<br>M src/southbridge/amd/sb800/early_setup.c<br>M src/southbridge/amd/sb800/reset.c<br>M src/southbridge/broadcom/bcm5785/Kconfig<br>M src/southbridge/broadcom/bcm5785/early_setup.c<br>M src/southbridge/broadcom/bcm5785/reset.c<br>M src/southbridge/nvidia/ck804/Kconfig<br>M src/southbridge/nvidia/ck804/early_setup.c<br>M src/southbridge/nvidia/ck804/early_setup_car.c<br>M src/southbridge/nvidia/ck804/reset.c<br>M src/southbridge/nvidia/mcp55/Kconfig<br>M src/southbridge/nvidia/mcp55/early_ctrl.c<br>M src/southbridge/nvidia/mcp55/reset.c<br>21 files changed, 12 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29058/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig</span><br><span>index 2d341db..f20cf21 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/Kconfig</span><br><span>+++ b/src/mainboard/asus/kcma-d8/Kconfig</span><br><span>@@ -17,7 +17,6 @@</span><br><span> select HAVE_ROMSTAGE_CONSOLE_SPINLOCK</span><br><span> select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK</span><br><span> select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_PIRQ_TABLE</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig</span><br><span>index 3e9f3f3..55bd5c3 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/Kconfig</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/Kconfig</span><br><span>@@ -9,7 +9,6 @@</span><br><span> select SOUTHBRIDGE_NVIDIA_CK804</span><br><span> select SUPERIO_WINBOND_W83627THG</span><br><span> select PARALLEL_CPU_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_PIRQ_TABLE</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig</span><br><span>index 531ba4f..8028849 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/Kconfig</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/Kconfig</span><br><span>@@ -17,7 +17,6 @@</span><br><span> select HAVE_ROMSTAGE_CONSOLE_SPINLOCK</span><br><span> select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK</span><br><span> select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_CMOS_DEFAULT</span><br><span> select HAVE_PIRQ_TABLE</span><br><span>diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig</span><br><span>index 5541c93..1436d8c 100644</span><br><span>--- a/src/southbridge/amd/amd8111/Kconfig</span><br><span>+++ b/src/southbridge/amd/amd8111/Kconfig</span><br><span>@@ -16,7 +16,6 @@</span><br><span> config SOUTHBRIDGE_AMD_AMD8111</span><br><span> bool</span><br><span> select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> </span><br><span> config BOOTBLOCK_SOUTHBRIDGE_INIT</span><br><span> string</span><br><span>diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>index f3ba8b6..aa323e4 100644</span><br><span>--- a/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>+++ b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>@@ -52,7 +52,7 @@</span><br><span> enable_cf9_x(sbbusn, sbdn);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> /* reset */</span><br><span>diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c</span><br><span>index fea8891..41d9880 100644</span><br><span>--- a/src/southbridge/amd/amd8111/reset.c</span><br><span>+++ b/src/southbridge/amd/amd8111/reset.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> </span><br><span> #include "../../../northbridge/amd/amdk8/reset_test.c"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> pci_devfn_t dev;</span><br><span> unsigned bus;</span><br><span>diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig</span><br><span>index 353c2a4..6d62e67 100644</span><br><span>--- a/src/southbridge/amd/sb700/Kconfig</span><br><span>+++ b/src/southbridge/amd/sb700/Kconfig</span><br><span>@@ -22,7 +22,6 @@</span><br><span> def_bool y</span><br><span> select IOAPIC</span><br><span> select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select SMBUS_HAS_AUX_CHANNELS</span><br><span> </span><br><span> config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI</span><br><span>diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c</span><br><span>index 0878039..f5f7a2c 100644</span><br><span>--- a/src/southbridge/amd/sb700/reset.c</span><br><span>+++ b/src/southbridge/amd/sb700/reset.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig</span><br><span>index f20fa82..d66469a 100644</span><br><span>--- a/src/southbridge/amd/sb800/Kconfig</span><br><span>+++ b/src/southbridge/amd/sb800/Kconfig</span><br><span>@@ -17,7 +17,6 @@</span><br><span> bool</span><br><span> select IOAPIC</span><br><span> select HAVE_USBDEBUG_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> </span><br><span> if SOUTHBRIDGE_AMD_SB800</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c</span><br><span>index badc4a7..d73b75d 100644</span><br><span>--- a/src/southbridge/amd/sb800/early_setup.c</span><br><span>+++ b/src/southbridge/amd/sb800/early_setup.c</span><br><span>@@ -218,7 +218,7 @@</span><br><span> pmio_write(0x81, byte);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c</span><br><span>index e3f36f3..bd578b6 100644</span><br><span>--- a/src/southbridge/amd/sb800/reset.c</span><br><span>+++ b/src/southbridge/amd/sb800/reset.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> </span><br><span> #include <northbridge/amd/amdk8/reset_test.c></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> /* Try rebooting through port 0xcf9 */</span><br><span>diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig</span><br><span>index d72afd8..1ec4f8f 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/Kconfig</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/Kconfig</span><br><span>@@ -1,6 +1,5 @@</span><br><span> config SOUTHBRIDGE_BROADCOM_BCM5785</span><br><span> bool</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> </span><br><span> config BOOTBLOCK_SOUTHBRIDGE_INIT</span><br><span> string</span><br><span>diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>index 766aa1a..c2aa9bc 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>@@ -103,7 +103,7 @@</span><br><span> }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> bcm5785_enable_wdt_port_cf9();</span><br><span> </span><br><span>diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c</span><br><span>index 1041aae..ad3ea8f 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/reset.c</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/reset.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> </span><br><span> #include "../../../northbridge/amd/amdk8/reset_test.c"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> /* Try rebooting through port 0xcf9 */</span><br><span>diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig</span><br><span>index dbd24b7..338357e 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/Kconfig</span><br><span>+++ b/src/southbridge/nvidia/ck804/Kconfig</span><br><span>@@ -1,6 +1,5 @@</span><br><span> config SOUTHBRIDGE_NVIDIA_CK804</span><br><span> bool</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select HAVE_USBDEBUG</span><br><span> select IOAPIC</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c</span><br><span>index 673c44d..30b68ec 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/early_setup.c</span><br><span>+++ b/src/southbridge/nvidia/ck804/early_setup.c</span><br><span>@@ -310,7 +310,7 @@</span><br><span> return set_ht_link_ck804(4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c</span><br><span>index 99e6ba7..fbc2719 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/early_setup_car.c</span><br><span>+++ b/src/southbridge/nvidia/ck804/early_setup_car.c</span><br><span>@@ -355,7 +355,7 @@</span><br><span> return set_ht_link_ck804(4);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c</span><br><span>index bcb6dfc..f828c53 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/reset.c</span><br><span>+++ b/src/southbridge/nvidia/ck804/reset.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> </span><br><span> #include "../../../northbridge/amd/amdk8/reset_test.c"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> /* Try rebooting through port 0xcf9. */</span><br><span>diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig</span><br><span>index 89aa452..bb1b7df 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/Kconfig</span><br><span>+++ b/src/southbridge/nvidia/mcp55/Kconfig</span><br><span>@@ -2,7 +2,6 @@</span><br><span> bool</span><br><span> select HAVE_USBDEBUG</span><br><span> select IOAPIC</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> </span><br><span> if SOUTHBRIDGE_NVIDIA_MCP55</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c</span><br><span>index e91abdf..66ceae2 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/early_ctrl.c</span><br><span>+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> outb(0x06, 0x0cf9);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c</span><br><span>index 7be98d7..d6f7f6f 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/reset.c</span><br><span>+++ b/src/southbridge/nvidia/mcp55/reset.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> #include "../../../northbridge/amd/amdk8/reset_test.c"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> set_bios_reset();</span><br><span> /* Try rebooting through port 0xcf9 */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29058">change 29058</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c </div>
<div style="display:none"> Gerrit-Change-Number: 29058 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>