<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29059">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">reset: Final moves to new API<br><br>Move soft_reset() to `southbridge/amd/common/` it's only used for<br>amdfam10 now.<br><br>Let common code call board_reset() instead of hard_reset() and drop<br>the latter for good.<br><br>Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/cpu/amd/family_10h-family_15h/init_cpus.c<br>M src/device/root_device.c<br>M src/include/reset.h<br>M src/lib/prog_loaders.c<br>M src/lib/reset.c<br>M src/mainboard/advansus/a785e-i/romstage.c<br>M src/mainboard/amd/bimini_fam10/romstage.c<br>M src/mainboard/amd/mahogany_fam10/romstage.c<br>M src/mainboard/amd/tilapia_fam10/romstage.c<br>M src/mainboard/asus/kcma-d8/romstage.c<br>M src/mainboard/asus/kfsn4-dre/romstage.c<br>M src/mainboard/asus/kgpe-d16/romstage.c<br>M src/mainboard/asus/m4a78-em/romstage.c<br>M src/mainboard/asus/m4a785-m/romstage.c<br>M src/mainboard/asus/m5a88-v/romstage.c<br>M src/mainboard/avalue/eax-785e/romstage.c<br>M src/mainboard/gigabyte/ma785gm/romstage.c<br>M src/mainboard/gigabyte/ma785gmt/romstage.c<br>M src/mainboard/gigabyte/ma78gm/romstage.c<br>M src/mainboard/hp/dl165_g6_fam10/romstage.c<br>M src/mainboard/iei/kino-780am2-fam10/romstage.c<br>M src/mainboard/jetway/pa78vm5/romstage.c<br>M src/mainboard/msi/ms9652_fam10/romstage.c<br>M src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>M src/mainboard/supermicro/h8qme_fam10/romstage.c<br>M src/mainboard/supermicro/h8scm_fam10/romstage.c<br>M src/mainboard/tyan/s2912_fam10/romstage.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>M src/security/vboot/vboot_common.c<br>M src/southbridge/amd/amd8111/early_ctrl.c<br>A src/southbridge/amd/common/reset.h<br>M src/southbridge/amd/sb700/reset.c<br>M src/southbridge/amd/sb800/early_setup.c<br>M src/southbridge/amd/sr5650/early_setup.c<br>M src/southbridge/broadcom/bcm5785/early_setup.c<br>M src/southbridge/nvidia/ck804/early_setup.c<br>M src/southbridge/nvidia/ck804/early_setup_car.c<br>M src/southbridge/nvidia/mcp55/early_ctrl.c<br>M src/vendorcode/google/chromeos/watchdog.c<br>39 files changed, 72 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29059/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>index 51cf510..9317368 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c</span><br><span>@@ -26,6 +26,8 @@</span><br><span> #include <northbridge/amd/amdht/porting.h></span><br><span> #include <northbridge/amd/amdht/h3ncmn.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)</span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #endif</span><br><span>diff --git a/src/device/root_device.c b/src/device/root_device.c</span><br><span>index b0b6712..e006bf9 100644</span><br><span>--- a/src/device/root_device.c</span><br><span>+++ b/src/device/root_device.c</span><br><span>@@ -147,7 +147,7 @@</span><br><span> static void root_dev_reset(struct bus *bus)</span><br><span> {</span><br><span> printk(BIOS_INFO, "Resetting board...\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span>diff --git a/src/include/reset.h b/src/include/reset.h</span><br><span>index 975a594..0b583cf 100644</span><br><span>--- a/src/include/reset.h</span><br><span>+++ b/src/include/reset.h</span><br><span>@@ -42,14 +42,4 @@</span><br><span> */</span><br><span> void do_board_reset(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */</span><br><span style="color: hsl(0, 100%, 40%);">-__noreturn void hard_reset(void);</span><br><span style="color: hsl(0, 100%, 40%);">-/* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */</span><br><span style="color: hsl(0, 100%, 40%);">-__noreturn void soft_reset(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Reset implementations. Implement these in SoC or mainboard code. Implement</span><br><span style="color: hsl(0, 100%, 40%);">- at least hard_reset() if possible, others fall back to it if necessary. */</span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void do_soft_reset(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif</span><br><span>diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c</span><br><span>index e3ddce0..2946dda 100644</span><br><span>--- a/src/lib/prog_loaders.c</span><br><span>+++ b/src/lib/prog_loaders.c</span><br><span>@@ -84,7 +84,7 @@</span><br><span> {</span><br><span> printk(BIOS_ERR, "ramstage cache invalid.\n");</span><br><span> if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) {</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> halt();</span><br><span> }</span><br><span> }</span><br><span>diff --git a/src/lib/reset.c b/src/lib/reset.c</span><br><span>index e93e14b..904776e 100644</span><br><span>--- a/src/lib/reset.c</span><br><span>+++ b/src/lib/reset.c</span><br><span>@@ -32,29 +32,3 @@</span><br><span> printk(BIOS_CRIT, "No board_reset implementation, hanging...\n");</span><br><span> }</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__noreturn static void __hard_reset(void) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))</span><br><span style="color: hsl(0, 100%, 40%);">- do_hard_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_CRIT, "No hard_reset implementation, hanging...\n");</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Not all platforms implement all reset types. Fall back to hard_reset. */</span><br><span style="color: hsl(0, 100%, 40%);">-__weak void do_soft_reset(void) { __hard_reset(); }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void hard_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- dcache_clean_all();</span><br><span style="color: hsl(0, 100%, 40%);">- __hard_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void soft_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- dcache_clean_all();</span><br><span style="color: hsl(0, 100%, 40%);">- do_soft_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- halt();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c</span><br><span>index e73a0e7..4aedad1 100644</span><br><span>--- a/src/mainboard/advansus/a785e-i/romstage.c</span><br><span>+++ b/src/mainboard/advansus/a785e-i/romstage.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb800/smbus.h></span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span> #include <southbridge/amd/rs780/rs780.h></span><br><span>@@ -49,7 +50,6 @@</span><br><span> #include "resourcemap.c"</span><br><span> #include "cpu/amd/quadcore/quadcore.c"</span><br><span> #include "spd.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> </span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c</span><br><span>index 5ee1fd6..9b89d9c 100644</span><br><span>--- a/src/mainboard/amd/bimini_fam10/romstage.c</span><br><span>+++ b/src/mainboard/amd/bimini_fam10/romstage.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb800/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span>diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c</span><br><span>index 0e2db04..1b11cfe 100644</span><br><span>--- a/src/mainboard/amd/mahogany_fam10/romstage.c</span><br><span>+++ b/src/mainboard/amd/mahogany_fam10/romstage.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #include <superio/ite/it8718f/it8718f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span>diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c</span><br><span>index 89e72eb..dd25582 100644</span><br><span>--- a/src/mainboard/amd/tilapia_fam10/romstage.c</span><br><span>+++ b/src/mainboard/amd/tilapia_fam10/romstage.c</span><br><span>@@ -37,6 +37,7 @@</span><br><span> #include <superio/ite/it8718f/it8718f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span>diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c</span><br><span>index 1d616a6..dc270e8 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/romstage.c</span><br><span>+++ b/src/mainboard/asus/kcma-d8/romstage.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <arch/io.h></span><br><span>@@ -38,6 +37,7 @@</span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <smp/spinlock.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <southbridge/amd/sr5650/sr5650.h></span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c</span><br><span>index 036f136..b31c043 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/romstage.c</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/romstage.c</span><br><span>@@ -22,7 +22,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <arch/io.h></span><br><span>@@ -35,6 +34,7 @@</span><br><span> #include <cbmem.h></span><br><span> #include <cpu/amd/model_10xxx_rev.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/nvidia/ck804/early_smbus.h></span><br><span> #include <delay.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>index 98bb1ca..cb1ce6f 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/romstage.c</span><br><span>@@ -19,7 +19,6 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <arch/io.h></span><br><span>@@ -38,6 +37,7 @@</span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <cpu/amd/car.h></span><br><span> #include <smp/spinlock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <southbridge/amd/sr5650/sr5650.h></span><br><span>diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c</span><br><span>index 4e05f0f..a45c7d1 100644</span><br><span>--- a/src/mainboard/asus/m4a78-em/romstage.c</span><br><span>+++ b/src/mainboard/asus/m4a78-em/romstage.c</span><br><span>@@ -38,6 +38,7 @@</span><br><span> #include <superio/ite/it8712f/it8712f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span>diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c</span><br><span>index b4f6293..ffa6789 100644</span><br><span>--- a/src/mainboard/asus/m4a785-m/romstage.c</span><br><span>+++ b/src/mainboard/asus/m4a785-m/romstage.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #include <superio/ite/it8712f/it8712f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span>diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c</span><br><span>index fb1a134..401df74 100644</span><br><span>--- a/src/mainboard/asus/m5a88-v/romstage.c</span><br><span>+++ b/src/mainboard/asus/m5a88-v/romstage.c</span><br><span>@@ -38,6 +38,7 @@</span><br><span> #include <superio/ite/it8721f/it8721f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb800/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span>@@ -47,7 +48,6 @@</span><br><span> #include <southbridge/amd/rs780/rs780.h></span><br><span> #include "southbridge/amd/sb800/early_setup.c"</span><br><span> #include "spd.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> </span><br><span> #include "resourcemap.c"</span><br><span> #include "cpu/amd/quadcore/quadcore.c"</span><br><span>diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c</span><br><span>index d91776c..da493bd 100644</span><br><span>--- a/src/mainboard/avalue/eax-785e/romstage.c</span><br><span>+++ b/src/mainboard/avalue/eax-785e/romstage.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <superio/winbond/w83627hf/w83627hf.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb800/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span>@@ -43,7 +44,6 @@</span><br><span> #include <arch/early_variables.h></span><br><span> #include <cbmem.h></span><br><span> #include "spd.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span> #include <southbridge/amd/rs780/rs780.h></span><br><span> #include <southbridge/amd/sb800/early_setup.c></span><br><span> </span><br><span>diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c</span><br><span>index 680d279..6c6da68 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gm/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ma785gm/romstage.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> #include <superio/ite/it8718f/it8718f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span>diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c</span><br><span>index 642f70b..ee7fb20 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gmt/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> #include <superio/ite/it8718f/it8718f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span>diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c</span><br><span>index 923cfbc..1fa5be3 100644</span><br><span>--- a/src/mainboard/gigabyte/ma78gm/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ma78gm/romstage.c</span><br><span>@@ -38,6 +38,7 @@</span><br><span> #include <superio/ite/it8718f/it8718f.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <spd.h></span><br><span>diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c</span><br><span>index fc922f4..95e8112 100644</span><br><span>--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c</span><br><span>+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c</span><br><span>@@ -48,6 +48,7 @@</span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span> #include <arch/early_variables.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "southbridge/broadcom/bcm5785/early_smbus.c"</span><br><span> #include "southbridge/broadcom/bcm5785/early_setup.c"</span><br><span> </span><br><span>diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c</span><br><span>index 5693cee..15d11a7 100644</span><br><span>--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c</span><br><span>+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c</span><br><span>@@ -38,6 +38,7 @@</span><br><span> #include <superio/fintek/f71859/f71859.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <spd.h></span><br><span>diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c</span><br><span>index 1041696..a81c6cc 100644</span><br><span>--- a/src/mainboard/jetway/pa78vm5/romstage.c</span><br><span>+++ b/src/mainboard/jetway/pa78vm5/romstage.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #include <superio/fintek/f71863fg/f71863fg.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <spd.h></span><br><span>diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c</span><br><span>index 7848e9e..9a02536 100644</span><br><span>--- a/src/mainboard/msi/ms9652_fam10/romstage.c</span><br><span>+++ b/src/mainboard/msi/ms9652_fam10/romstage.c</span><br><span>@@ -41,6 +41,7 @@</span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span> #include <arch/early_variables.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/nvidia/mcp55/mcp55.h></span><br><span> </span><br><span> #include "resourcemap.c"</span><br><span>diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c</span><br><span>index d5506df..2e793bb 100644</span><br><span>--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <superio/winbond/w83627hf/w83627hf.h></span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span>diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>index f438400..57cd17d 100644</span><br><span>--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <superio/winbond/w83627hf/w83627hf.h></span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span>diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c</span><br><span>index a3d3cea..b8eae83 100644</span><br><span>--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c</span><br><span>+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <cpu/amd/car.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <southbridge/amd/sb700/sb700.h></span><br><span> #include <southbridge/amd/sb700/smbus.h></span><br><span> #include <southbridge/amd/sr5650/sr5650.h></span><br><span>diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c</span><br><span>index 0b47f9d..2764820 100644</span><br><span>--- a/src/mainboard/tyan/s2912_fam10/romstage.c</span><br><span>+++ b/src/mainboard/tyan/s2912_fam10/romstage.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <superio/winbond/common/winbond.h></span><br><span> #include <superio/winbond/w83627hf/w83627hf.h></span><br><span> #include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdht/ht_wrapper.h></span><br><span> #include <cpu/amd/family_10h-family_15h/init_cpus.h></span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>index 7421c18..12c1f60 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> #include <northbridge/amd/amdfam10/debug.h></span><br><span> #include <northbridge/amd/amdfam10/raminit.h></span><br><span> #include <northbridge/amd/amdfam10/amdfam10.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <arch/acpi.h></span><br><span> #include <string.h></span><br><span>diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c</span><br><span>index 901f126..ae2ae77 100644</span><br><span>--- a/src/security/vboot/vboot_common.c</span><br><span>+++ b/src/security/vboot/vboot_common.c</span><br><span>@@ -129,6 +129,6 @@</span><br><span> if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))</span><br><span> cbmem_dump_console();</span><br><span> vboot_platform_prepare_reboot();</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> die("failed to reboot");</span><br><span> }</span><br><span>diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>index aa323e4..7315d01 100644</span><br><span>--- a/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>+++ b/src/southbridge/amd/amd8111/early_ctrl.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include "amd8111.h"</span><br><span> #include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> </span><br><span> unsigned get_sbdn(unsigned bus)</span><br><span> {</span><br><span>diff --git a/src/southbridge/amd/common/reset.h b/src/southbridge/amd/common/reset.h</span><br><span>new file mode 100644</span><br><span>index 0000000..ce101cb</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/amd/common/reset.h</span><br><span>@@ -0,0 +1,35 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Google, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _AMD_SB_RESET_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _AMD_SB_RESET_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Implement the bare reset, e.g. write to cf9. */</span><br><span style="color: hsl(120, 100%, 40%);">+void do_soft_reset(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Prepare for reset, run do_soft_reset(), halt. */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline __noreturn void soft_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "%s() called!\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ dcache_clean_all();</span><br><span style="color: hsl(120, 100%, 40%);">+ do_soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ halt();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _AMD_SB_RESET_H_ */</span><br><span>diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c</span><br><span>index f5f7a2c..4c9b0f4 100644</span><br><span>--- a/src/southbridge/amd/sb700/reset.c</span><br><span>+++ b/src/southbridge/amd/sb700/reset.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> </span><br><span> #define HT_INIT_CONTROL 0x6C</span><br><span> #define HTIC_BIOSR_Detect (1<<5)</span><br><span>diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c</span><br><span>index d73b75d..b6dfc39 100644</span><br><span>--- a/src/southbridge/amd/sb800/early_setup.c</span><br><span>+++ b/src/southbridge/amd/sb800/early_setup.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <reset.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <southbridge/amd/common/amd_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "sb800.h"</span><br><span> #include "smbus.c"</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c</span><br><span>index 96adfb5..484d9fc 100644</span><br><span>--- a/src/southbridge/amd/sr5650/early_setup.c</span><br><span>+++ b/src/southbridge/amd/sr5650/early_setup.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/msr.h></span><br><span> #include <option.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "sr5650.h"</span><br><span> #include "cmn.h"</span><br><span> </span><br><span>diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>index c2aa9bc..df7217c 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/early_setup.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "bcm5785.h"</span><br><span> </span><br><span> static void bcm5785_enable_lpc(void)</span><br><span>diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c</span><br><span>index 30b68ec..0d92bfc 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/early_setup.c</span><br><span>+++ b/src/southbridge/nvidia/ck804/early_setup.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "ck804.h"</span><br><span> </span><br><span> static int set_ht_link_ck804(u8 ht_c_num)</span><br><span>diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c</span><br><span>index fbc2719..266b97c 100644</span><br><span>--- a/src/southbridge/nvidia/ck804/early_setup_car.c</span><br><span>+++ b/src/southbridge/nvidia/ck804/early_setup_car.c</span><br><span>@@ -16,6 +16,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "ck804.h"</span><br><span> </span><br><span> /* Someone messed up and snuck in some K8-specific code */</span><br><span>diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c</span><br><span>index 66ceae2..c142249 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/early_ctrl.c</span><br><span>+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <reset.h></span><br><span> #include <northbridge/amd/amdfam10/amdfam10.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/amd/common/reset.h></span><br><span> #include "mcp55.h"</span><br><span> </span><br><span> void do_soft_reset(void)</span><br><span>diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c</span><br><span>index fdaa177..61619ce 100644</span><br><span>--- a/src/vendorcode/google/chromeos/watchdog.c</span><br><span>+++ b/src/vendorcode/google/chromeos/watchdog.c</span><br><span>@@ -52,5 +52,5 @@</span><br><span> {</span><br><span> printk(BIOS_INFO, "Last reset was watchdog, reboot again to reset TPM!\n");</span><br><span> mark_watchdog_tombstone();</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29059">change 29059</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29059"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e </div>
<div style="display:none"> Gerrit-Change-Number: 29059 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>