<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29049">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/rockchip/rk3399: Convert to `board_reset()`<br><br>Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/mainboard/google/gru/Kconfig<br>M src/mainboard/google/gru/reset.c<br>M src/soc/rockchip/rk3399/sdram.c<br>3 files changed, 6 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29049/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig</span><br><span>index 11bf18c..fee2dd0 100644</span><br><span>--- a/src/mainboard/google/gru/Kconfig</span><br><span>+++ b/src/mainboard/google/gru/Kconfig</span><br><span>@@ -47,7 +47,6 @@</span><br><span> select EC_GOOGLE_CHROMEEC</span><br><span> select EC_GOOGLE_CHROMEEC_RTC</span><br><span> select EC_GOOGLE_CHROMEEC_SPI</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_HARD_RESET</span><br><span> select MAINBOARD_FORCE_NATIVE_VGA_INIT</span><br><span> select MAINBOARD_HAS_CHROMEOS</span><br><span> select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span>diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c</span><br><span>index 0311d58..5bf7260 100644</span><br><span>--- a/src/mainboard/google/gru/reset.c</span><br><span>+++ b/src/mainboard/google/gru/reset.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> </span><br><span> #include "board.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void do_hard_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void do_board_reset(void)</span><br><span> {</span><br><span> gpio_output(GPIO_RESET, 1);</span><br><span> }</span><br><span>diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c</span><br><span>index 9734679..2b08413 100644</span><br><span>--- a/src/soc/rockchip/rk3399/sdram.c</span><br><span>+++ b/src/soc/rockchip/rk3399/sdram.c</span><br><span>@@ -990,7 +990,7 @@</span><br><span> if (stopwatch_expired(&sw)) {</span><br><span> printk(BIOS_ERR,</span><br><span> "index1 frequency change overtime, reset\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -1000,7 +1000,7 @@</span><br><span> if (stopwatch_expired(&sw)) {</span><br><span> printk(BIOS_ERR,</span><br><span> "index1 frequency done overtime, reset\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -1009,7 +1009,7 @@</span><br><span> clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);</span><br><span> if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {</span><br><span> printk(BIOS_ERR, "index1 training failed, reset\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span> }</span><br><span> }</span><br><span>@@ -1042,7 +1042,7 @@</span><br><span> */</span><br><span> if (pctl_cfg(channel, sdram_params) != 0) {</span><br><span> printk(BIOS_ERR, "pctl_cfg fail, reset\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span> </span><br><span> /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */</span><br><span>@@ -1052,7 +1052,7 @@</span><br><span> if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {</span><br><span> printk(BIOS_ERR,</span><br><span> "SDRAM initialization failed, reset\n");</span><br><span style="color: hsl(0, 100%, 40%);">- hard_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ board_reset();</span><br><span> }</span><br><span> </span><br><span> set_ddrconfig(sdram_params, channel,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29049">change 29049</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29049"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 </div>
<div style="display:none"> Gerrit-Change-Number: 29049 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>