<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29023">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: add support smp_pause / smp_resume<br><br>See https://doc.coreboot.org/arch/riscv/ we know that we need to execute<br>smp_pause at the start of each stage and smp_resume at the end of each<br>stage.<br><br>Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/Kconfig<br>A src/arch/riscv/include/arch/smp/smp.h<br>M src/arch/riscv/include/mcall.h<br>3 files changed, 66 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29023/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig</span><br><span>index 2d53f42..96179a5 100644</span><br><span>--- a/src/arch/riscv/Kconfig</span><br><span>+++ b/src/arch/riscv/Kconfig</span><br><span>@@ -32,3 +32,7 @@</span><br><span> config RISCV_USE_ARCH_TIMER</span><br><span> bool</span><br><span> default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config RISCV_HART_NUM</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h</span><br><span>new file mode 100644</span><br><span>index 0000000..7431142</span><br><span>--- /dev/null</span><br><span>+++ b/src/arch/riscv/include/arch/smp/smp.h</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 HardenedLinux.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _RISCV_SMP_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _RISCV_SMP_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/encoding.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/spinlock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <mcall.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void set_msip(int hartid, int val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void smp_pause(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read_csr(mhartid) == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ clear_csr(mstatus, MSTATUS_MIE);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_csr(mie, MIP_MSIP);</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ barrier();</span><br><span style="color: hsl(120, 100%, 40%);">+ __asm__ volatile ("wfi");</span><br><span style="color: hsl(120, 100%, 40%);">+ } while ((read_csr(mip) & MIP_MSIP) == 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_msip(read_csr(mhartid), 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ HLS()->entry.fn(HLS()->entry.arg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void smp_resume(void (*fn)(void *), void *arg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int hartid = read_csr(mhartid);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ OTHER_HLS(i)->entry.fn = fn;</span><br><span style="color: hsl(120, 100%, 40%);">+ OTHER_HLS(i)->entry.arg = arg;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (i != hartid)</span><br><span style="color: hsl(120, 100%, 40%);">+ set_msip(i, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ HLS()->entry.fn(HLS()->entry.arg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h</span><br><span>index d1e414a..3e559f7 100644</span><br><span>--- a/src/arch/riscv/include/mcall.h</span><br><span>+++ b/src/arch/riscv/include/mcall.h</span><br><span>@@ -18,7 +18,7 @@</span><br><span> </span><br><span> // NOTE: this is the size of hls_t below. A static_assert would be</span><br><span> // nice to have.</span><br><span style="color: hsl(0, 100%, 40%);">-#define HLS_SIZE 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define HLS_SIZE 80</span><br><span> </span><br><span> /* We save 37 registers, currently. */</span><br><span> #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)</span><br><span>@@ -35,6 +35,10 @@</span><br><span> unsigned long sbi_private_data;</span><br><span> } sbi_device_message;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct blocker {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *arg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void (*fn)(void *arg);</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span> </span><br><span> typedef struct {</span><br><span> sbi_device_message *device_request_queue_head;</span><br><span>@@ -46,6 +50,7 @@</span><br><span> int ipi_pending;</span><br><span> uint64_t *timecmp;</span><br><span> uint64_t *time;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct blocker entry;</span><br><span> } hls_t;</span><br><span> </span><br><span> #define MACHINE_STACK_TOP() ({ \</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29023">change 29023</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb </div>
<div style="display:none"> Gerrit-Change-Number: 29023 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>