<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29014">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Rename GppClkCntrl fields<br><br>Make the field names of the MISCx00 GPPClkCntrl more manageable by<br>shortening their names. Make the definitions look more like the<br>rest of the header file.<br><br>Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/mainboard/google/kahlee/mainboard.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>2 files changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29014/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c</span><br><span>index bfd1f2f..ebdcc93 100644</span><br><span>--- a/src/mainboard/google/kahlee/mainboard.c</span><br><span>+++ b/src/mainboard/google/kahlee/mainboard.c</span><br><span>@@ -146,15 +146,15 @@</span><br><span> </span><br><span> /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */</span><br><span> clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),</span><br><span style="color: hsl(0, 100%, 40%);">- GPP_CLK2_CLOCK_REQ_MAP_MASK,</span><br><span style="color: hsl(0, 100%, 40%);">- GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<</span><br><span style="color: hsl(0, 100%, 40%);">- GPP_CLK2_CLOCK_REQ_MAP_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK2_REQ_MAP_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK2_REQ_MAP_CLK_REQ2 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK2_REQ_MAP_SHIFT);</span><br><span> </span><br><span> /* Same for the WiFi */</span><br><span> clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),</span><br><span style="color: hsl(0, 100%, 40%);">- GPP_CLK0_CLOCK_REQ_MAP_MASK,</span><br><span style="color: hsl(0, 100%, 40%);">- GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<</span><br><span style="color: hsl(0, 100%, 40%);">- GPP_CLK0_CLOCK_REQ_MAP_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK0_REQ_MAP_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK0_REQ_MAP_CLK_REQ0 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK0_REQ_MAP_SHIFT);</span><br><span> }</span><br><span> </span><br><span> /*************************************************</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index d25c90b..7f02811 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -111,13 +111,13 @@</span><br><span> </span><br><span> /* FCH MISC Registers 0xfed80e00 */</span><br><span> #define GPP_CLK_CNTRL 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_REQ_MAP_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_REQ_MAP_CLK_REQ2 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_REQ_MAP_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_REQ_MAP_CLK_REQ0 1</span><br><span> </span><br><span> #define MISC_CGPLL_CONFIG1 0x08</span><br><span> #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29014">change 29014</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29014"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 </div>
<div style="display:none"> Gerrit-Change-Number: 29014 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>