<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29013">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Rearrange southbridge.h<br><br>Group definitions so they're near others of the same type, e.g. PCI,<br>AcpiMmio, etc.<br><br>Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>1 file changed, 212 insertions(+), 204 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29013/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 0aeb0fc..d25c90b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -26,10 +26,10 @@</span><br><span> #include "chip.h"</span><br><span> #include <rules.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* PSP at D8F0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PSP_BAR_ENABLES 0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define PSP_MAILBOX_BAR_EN 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * AcpiMmio Region</span><br><span style="color: hsl(120, 100%, 40%);">+ * - fixed addresses offset from 0xfed80000</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> </span><br><span> /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */</span><br><span> #define PM_DECODE_EN 0x00</span><br><span>@@ -40,6 +40,10 @@</span><br><span> #define PM_PCI_CTRL 0x08</span><br><span> #define FORCE_SLPSTATE_RETRY BIT(25)</span><br><span> #define FORCE_STPCLK_RETRY BIT(24)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PWR_RESET_CFG 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOGGLE_ALL_PWR_GOOD BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PM_SERIRQ_CONF 0x54</span><br><span> #define PM_SERIRQ_NUM_BITS_17 0x0000</span><br><span> #define PM_SERIRQ_NUM_BITS_18 0x0004</span><br><span>@@ -105,179 +109,36 @@</span><br><span> #define SPI_ROM_ALT_ENABLE BIT(0)</span><br><span> #define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_PCI_CONTROL 0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define LEGACY_DMA_EN BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+/* FCH MISC Registers 0xfed80e00 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK_CNTRL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_IO_PORT_DECODE_ENABLE 0x44</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT0 BIT(6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT1 BIT(7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT2 BIT(8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT3 BIT(9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT4 BIT(10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT5 BIT(11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT6 BIT(12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_SERIAL_PORT7 BIT(13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_AUDIO_PORT0 BIT(14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_AUDIO_PORT1 BIT(15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_AUDIO_PORT2 BIT(16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_AUDIO_PORT3 BIT(17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MIDI_PORT0 BIT(18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MIDI_PORT1 BIT(19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MIDI_PORT2 BIT(20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MIDI_PORT3 BIT(21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MSS_PORT0 BIT(22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MSS_PORT1 BIT(23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MSS_PORT2 BIT(24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_MSS_PORT3 BIT(25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_FDC_PORT0 BIT(26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_FDC_PORT1 BIT(27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_GAME_PORT BIT(28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_KBC_PORT BIT(29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_ACPIUC_PORT BIT(30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ENABLE_ADLIB_PORT BIT(31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO2_ENABLE BIT(25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO1_ENABLE BIT(24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE6 BIT(23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE5 BIT(22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE4 BIT(21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_MEM_PORT_ENABLE1 BIT(20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE3 BIT(19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE2 BIT(18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE1 BIT(17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE0 BIT(16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_DECODE_RTC_IO_ENABLE BIT(6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_MEM_PORT_ENABLE0 BIT(5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO0_ENABLE BIT(2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_ALTERNATE_SIO_ENABLE BIT(1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_SIO_ENABLE BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-/* Assuming word access to higher word (register 0x4a) */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO2_ENABLE_H BIT(9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO1_ENABLE_H BIT(8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE6_H BIT(7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE5_H BIT(6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE4_H BIT(5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE3_H BIT(3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE2_H BIT(2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE1_H BIT(1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DECODE_IO_PORT_ENABLE0_H BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_MEM_PORT1 0x4c</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_MEM_PORT0 0x60</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Register 0x64 is 32-bit, composed by two 16-bit sub-registers.</span><br><span style="color: hsl(0, 100%, 40%);">- * For ease of access, each sub-register is declared separetely.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO_GENERIC_PORT 0x64</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO1_GENERIC_PORT 0x66</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROM_ADDRESS_RANGE1_START 0x68</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROM_ADDRESS_RANGE1_END 0x6a</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROM_ADDRESS_RANGE2_START 0x6c</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROM_ADDRESS_RANGE2_END 0x6e</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_ALT_WIDEIO2_ENABLE BIT(3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_ALT_WIDEIO1_ENABLE BIT(2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_ALT_WIDEIO0_ENABLE BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_MISC_CONTROL_BITS 0x78</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_NOHOG BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_TRUSTED_PLATFORM_MODULE 0x7c</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_12_EN BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_LEGACY_EN BIT(2)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_WIDEIO2_GENERIC_PORT 0x90</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * LPC register 0xb8 is DWORD, here there are definitions for byte</span><br><span style="color: hsl(0, 100%, 40%);">- * access. For example, bits 31-24 are accessed through byte access</span><br><span style="color: hsl(0, 100%, 40%);">- * at register 0xbb ().</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FROM_HOST_PREFETCH_EN BIT(24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FROM_USB_PREFETCH_EN BIT(23)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LPC_HOST_CONTROL 0xbb</span><br><span style="color: hsl(0, 100%, 40%);">-#define PREFETCH_EN_SPI_FROM_HOST BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define T_START_ENH BIT(3)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI Controller */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CNTRL0 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_BUSY BIT(31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))</span><br><span style="color: hsl(0, 100%, 40%);">-/* Nominal is 16.7MHz on older devices, 33MHz on newer */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_NOM 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_DUAL112 ( BIT(29) )</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_DUAL122 (BIT(30) )</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO_PTR_CLR BIT(20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_ARB_ENABLE BIT(19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EXEC_OPCODE BIT(16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CNTRL1 0x0c</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CMD_CODE 0x45</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CMD_TRIGGER 0x47</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CMD_TRIGGER_EXECUTE BIT(7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_TX_BYTE_COUNT 0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_RX_BYTE_COUNT 0x4b</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_STATUS 0x4c</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_DONE_BYTE_COUNT_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_DONE_BYTE_COUNT_MASK 0xff</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO_WR_PTR_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO_WR_PTR_MASK 0x7f</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO_RD_PTR_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO_RD_PTR_MASK 0x7f</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO 0x80</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI100_SPEED_CONFIG 0x22</span><br><span style="color: hsl(0, 100%, 40%);">-/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_NORM_SPEED_SH 12</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FAST_SPEED_SH 8</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI100_ENABLE 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_USE_SPI100 BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI100_SPEED_CONFIG 0x22</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_SPEED_66M (0x0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_SPEED_33M ( BIT(0))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_SPEED_22M ( BIT(1) )</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_SPEED_16M ( BIT(1) | BIT(0))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_SPEED_100M (BIT(2) )</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_SPEED_800K (BIT(2) | BIT(0))</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_NORM_SPEED_NEW_SH 12</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_FAST_SPEED_NEW_SH 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_ALT_SPEED_NEW_SH 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_TPM_SPEED_NEW_SH 0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI100_HOST_PREF_CONFIG 0x2c</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_RD4DW_EN_HOST BIT(15)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_MISC_CLK_CNTL_1 0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* IO 0xcf9 - Reset control port*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define FULL_RST BIT(3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RST_CMD BIT(2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SYS_RST BIT(1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* PMx10 - Power Reset Config */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PWR_RESET_CFG 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOGGLE_ALL_PWR_GOOD BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG1 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG3 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_REFDIV_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_SHIFT 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG4 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG5 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG6 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_LF_MODE_SHIFT 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CLK_CNTL1 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define CG1PLL_FBDIV_TEST BIT(26)</span><br><span> </span><br><span> /* XHCI_PM Registers: 0xfed81c00 */</span><br><span> #define XHCI_PM_INDIRECT_INDEX 0x48</span><br><span>@@ -351,37 +212,184 @@</span><br><span> #define GPE0_LIMIT 28</span><br><span> #define TOTAL_BITS(a) (8 * sizeof(a))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK_CNTRL 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCI Config Space Definitions</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISA Bridge D14F3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_PCI_CONTROL 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define LEGACY_DMA_EN BIT(2)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Bit definitions for MISC_MMIO_BASE register MiscClkCntl1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG1 0x08</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG3 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_REFDIV_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_FBDIV_SHIFT 10</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG4 0x14</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG5 0x18</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG6 0x1c</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_LF_MODE_SHIFT 9</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CLK_CNTL1 0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define CG1PLL_FBDIV_TEST BIT(26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_IO_PORT_DECODE_ENABLE 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT0 BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT1 BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT2 BIT(8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT3 BIT(9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT4 BIT(10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT5 BIT(11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT6 BIT(12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_SERIAL_PORT7 BIT(13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_AUDIO_PORT0 BIT(14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_AUDIO_PORT1 BIT(15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_AUDIO_PORT2 BIT(16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_AUDIO_PORT3 BIT(17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MIDI_PORT0 BIT(18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MIDI_PORT1 BIT(19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MIDI_PORT2 BIT(20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MIDI_PORT3 BIT(21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MSS_PORT0 BIT(22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MSS_PORT1 BIT(23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MSS_PORT2 BIT(24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_MSS_PORT3 BIT(25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_FDC_PORT0 BIT(26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_FDC_PORT1 BIT(27)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_GAME_PORT BIT(28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_KBC_PORT BIT(29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_ACPIUC_PORT BIT(30)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ENABLE_ADLIB_PORT BIT(31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO2_ENABLE BIT(25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO1_ENABLE BIT(24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE6 BIT(23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE5 BIT(22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE4 BIT(21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_MEM_PORT_ENABLE1 BIT(20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE3 BIT(19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE2 BIT(18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE1 BIT(17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE0 BIT(16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DECODE_RTC_IO_ENABLE BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_MEM_PORT_ENABLE0 BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO0_ENABLE BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_ALTERNATE_SIO_ENABLE BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_SIO_ENABLE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define WIDEIO_RANGE_ERROR -1</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOTAL_WIDEIO_PORTS 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Assuming word access to higher word (register 0x4a) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO2_ENABLE_H BIT(9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO1_ENABLE_H BIT(8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE6_H BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE5_H BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE4_H BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE3_H BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE2_H BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE1_H BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DECODE_IO_PORT_ENABLE0_H BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_MEM_PORT1 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_MEM_PORT0 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers.</span><br><span style="color: hsl(120, 100%, 40%);">+ For ease of access, each sub-register is declared separetely. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO_GENERIC_PORT 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO1_GENERIC_PORT 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROM_ADDRESS_RANGE1_START 0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROM_ADDRESS_RANGE1_END 0x6a</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROM_ADDRESS_RANGE2_START 0x6c</span><br><span style="color: hsl(120, 100%, 40%);">+#define ROM_ADDRESS_RANGE2_END 0x6e</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_ALT_WIDEIO2_ENABLE BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_ALT_WIDEIO1_ENABLE BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_ALT_WIDEIO0_ENABLE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_MISC_CONTROL_BITS 0x78</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_NOHOG BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_TRUSTED_PLATFORM_MODULE 0x7c</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_12_EN BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_LEGACY_EN BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_WIDEIO2_GENERIC_PORT 0x90</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC register 0xb8 is DWORD, here there are definitions for byte</span><br><span style="color: hsl(120, 100%, 40%);">+ access. For example, bits 31-24 are accessed through byte access</span><br><span style="color: hsl(120, 100%, 40%);">+ at register 0xbb. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FROM_HOST_PREFETCH_EN BIT(24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FROM_USB_PREFETCH_EN BIT(23)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_HOST_CONTROL 0xbb</span><br><span style="color: hsl(120, 100%, 40%);">+#define PREFETCH_EN_SPI_FROM_HOST BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define T_START_ENH BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI Controller (base address in D14F3xA0) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CNTRL0 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_BUSY BIT(31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))</span><br><span style="color: hsl(120, 100%, 40%);">+/* Nominal is 16.7MHz on older devices, 33MHz on newer */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_NOM 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_DUAL112 ( BIT(29) )</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_DUAL122 (BIT(30) )</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO_PTR_CLR BIT(20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_ARB_ENABLE BIT(19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define EXEC_OPCODE BIT(16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CNTRL1 0x0c</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CMD_CODE 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CMD_TRIGGER 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CMD_TRIGGER_EXECUTE BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_TX_BYTE_COUNT 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_RX_BYTE_COUNT 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_STATUS 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_DONE_BYTE_COUNT_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_DONE_BYTE_COUNT_MASK 0xff</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO_WR_PTR_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO_WR_PTR_MASK 0x7f</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO_RD_PTR_SHIFT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO_RD_PTR_MASK 0x7f</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI100_SPEED_CONFIG 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_NORM_SPEED_SH 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FAST_SPEED_SH 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI100_ENABLE 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_USE_SPI100 BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI100_SPEED_CONFIG 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SPEED_66M (0x0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SPEED_33M ( BIT(0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SPEED_22M ( BIT(1) )</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SPEED_16M ( BIT(1) | BIT(0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SPEED_100M (BIT(2) )</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_SPEED_800K (BIT(2) | BIT(0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_NORM_SPEED_NEW_SH 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_FAST_SPEED_NEW_SH 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_ALT_SPEED_NEW_SH 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_TPM_SPEED_NEW_SH 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI100_HOST_PREF_CONFIG 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_RD4DW_EN_HOST BIT(15)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_MISC_CLK_CNTL_1 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Platform Security Processor D8F0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_BAR_ENABLES 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define PSP_MAILBOX_BAR_EN 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IO 0xcf9 - Reset control port*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define FULL_RST BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RST_CMD BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SYS_RST BIT(1)</span><br><span> </span><br><span> struct stoneyridge_aoac {</span><br><span> int enable;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29013">change 29013</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29013"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe </div>
<div style="display:none"> Gerrit-Change-Number: 29013 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>