<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29011">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Clarify XHCI_PM register definitions<br><br>Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>1 file changed, 16 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/29011/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index d4af8a1..ce3660b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -279,27 +279,26 @@</span><br><span> #define PWR_RESET_CFG 0x10</span><br><span> #define TOGGLE_ALL_PWR_GOOD BIT(1)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* XHCI_PM Registers: 0xfed81c00 */</span><br><span> #define XHCI_PM_INDIRECT_INDEX 0x48</span><br><span> #define XHCI_PM_INDIRECT_DATA 0x4c</span><br><span> #define XHCI_OVER_CURRENT_CONTROL 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC1 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC2 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC3 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC4 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC5 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC6 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC7 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC_DISABLE 0xf</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_OC_DISABLE_ALL 0xffff</span><br><span style="color: hsl(120, 100%, 40%);">+#define OC_PORT0_SHIFT 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define OC_PORT1_SHIFT 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define OC_PORT2_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define OC_PORT3_SHIFT 12</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define EHCI_OVER_CURRENT_CONTROL 0x70</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC0 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC1 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC2 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC3 3</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC4 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC5 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC6 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC7 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC_DISABLE 0xf</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_OC_DISABLE_ALL 0xffff</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define OC_PORT0_SHIFT 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define OC_PORT1_SHIFT 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define OC_PORT2_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define OC_PORT3_SHIFT 12</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define EHCI_HUB_CONFIG4 0x90</span><br><span> #define DEBUG_PORT_SELECT_SHIFT 16</span><br><span> #define DEBUG_PORT_ENABLE BIT(18)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29011">change 29011</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29011"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1b44ffd7c0244b0408c3823d634a9b8d5038462f </div>
<div style="display:none"> Gerrit-Change-Number: 29011 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>