<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28986">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/cavium/cn8100_sff_evb: Only expose two UARTs<br><br>Only two UARTs are connected to the FTDI UART USB chip.<br><br>Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/mainboard/cavium/cn8100_sff_evb/devicetree.cb<br>1 file changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28986/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb</span><br><span>index 3398e9a..00be155 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb</span><br><span>@@ -93,11 +93,11 @@</span><br><span>                           end</span><br><span>                          chip soc/cavium/common/pci</span><br><span>                                   register "secure" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-                                     device pci 08.2 on end # UUA2</span><br><span style="color: hsl(120, 100%, 40%);">+                                 device pci 08.2 off end # UUA2</span><br><span>                               end</span><br><span>                          chip soc/cavium/common/pci</span><br><span>                                   register "secure" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-                                     device pci 08.3 on end # UUA3</span><br><span style="color: hsl(120, 100%, 40%);">+                                 device pci 08.3 off end # UUA3</span><br><span>                               end</span><br><span>                          chip soc/cavium/common/pci</span><br><span>                                   register "secure" = "1"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28986">change 28986</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28986"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a </div>
<div style="display:none"> Gerrit-Change-Number: 28986 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>