<p>David Wu has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28963">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/fizz: Add variant API for gpio<br><br>Provide API for gpio table functionality. Default weak<br>implementations are provided from the baseboard.<br><br>BUG=b:117066935<br>BRANCH=Fizz<br>TEST=emerge-fizz coreboot<br><br>Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314<br>Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com><br>---<br>M src/mainboard/google/fizz/bootblock.c<br>M src/mainboard/google/fizz/ramstage.c<br>A src/mainboard/google/fizz/variants/baseboard/Makefile.inc<br>A src/mainboard/google/fizz/variants/baseboard/gpio.c<br>M src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h<br>A src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h<br>6 files changed, 315 insertions(+), 248 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/28963/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/fizz/bootblock.c b/src/mainboard/google/fizz/bootblock.c</span><br><span>index 4114cd5..ce669cc 100644</span><br><span>--- a/src/mainboard/google/fizz/bootblock.c</span><br><span>+++ b/src/mainboard/google/fizz/bootblock.c</span><br><span>@@ -13,17 +13,17 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span> #include <bootblock_common.h></span><br><span> #include <soc/gpio.h></span><br><span> </span><br><span> #include <variant/gpio.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void early_config_gpio(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void bootblock_mainboard_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- early_config_gpio();</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pads = variant_early_gpio_table(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(pads, num);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/fizz/ramstage.c b/src/mainboard/google/fizz/ramstage.c</span><br><span>index e208a67..d42f68c 100644</span><br><span>--- a/src/mainboard/google/fizz/ramstage.c</span><br><span>+++ b/src/mainboard/google/fizz/ramstage.c</span><br><span>@@ -13,6 +13,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span> #include <bootmode.h></span><br><span> #include <console/console.h></span><br><span> #include <delay.h></span><br><span>@@ -50,6 +51,8 @@</span><br><span> </span><br><span> void mainboard_silicon_init_params(FSP_SIL_UPD *params)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t num;</span><br><span> static const long display_timeout_ms = 3000;</span><br><span> </span><br><span> /* This is reconfigured back to whatever FSP-S expects by</span><br><span>@@ -61,5 +64,6 @@</span><br><span> wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));</span><br><span style="color: hsl(120, 100%, 40%);">+ pads = variant_gpio_table(&num);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_configure_pads(pads, num);</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/fizz/variants/baseboard/Makefile.inc b/src/mainboard/google/fizz/variants/baseboard/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..9fb63f5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/baseboard/Makefile.inc</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..5c8e9d0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c</span><br><span>@@ -0,0 +1,268 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Leave eSPI pins untouched from default settings */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE), /* SD_CDZ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* eSPI mode */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_RESET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* CLK_PCIE_LAN_REQ# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCIE_CLKREQ_SSD# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCIE_CLKREQ_NGFF1# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCIE_CLKREQ_WLAN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* VR_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* HWA_TRST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_NC(GPP_C2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0CLK */ PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* EC_IN_RW */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO4 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_NC(GPP_C18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SCREW_SPI_WP_STATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLTRST, EDGE), /* HP_IRQ_GPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* OEM_ID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* OEM_ID2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* OEM_ID3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLTRST), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* MB_PCIE_SATA#_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* DB_PCIE_SATA#_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* Rear Dual-Stack USB Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* Front USB Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* Rear Single USB Port */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* INT_HDMI_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* DDI2_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* HDMI_DDCCLK_SW */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* HDMI_DDCCLK_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_H1_3V3_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_H1_3V3_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SCL */ PAD_CFG_NC(GPP_F9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_AUDIO_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_AUDIO_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* RSVD */ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* RSVD */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLTRST), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Ensure UART pins are in native mode for H1. */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SCREW_SPI_WP_STATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* MB_PCIE_SATA#_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config * __attribute__((weak)) variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config * __attribute__((weak))</span><br><span style="color: hsl(120, 100%, 40%);">+ variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h</span><br><span>index 05d9d03..f5bcc74 100644</span><br><span>--- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h</span><br><span>+++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -42,245 +42,4 @@</span><br><span> #define GPIO_OEM_ID2 GPP_D11</span><br><span> #define GPIO_OEM_ID3 GPP_D12</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-/* Pad configuration in ramstage */</span><br><span style="color: hsl(0, 100%, 40%);">-/* Leave eSPI pins untouched from default settings */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_IO3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_CS# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- EDGE), /* SD_CDZ */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* eSPI mode */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ESPI_RESET# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* CLK_PCIE_LAN_REQ# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCIE_CLKREQ_SSD# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCIE_CLKREQ_NGFF1# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCIE_CLKREQ_WLAN# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* VR_DISABLE_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* HWA_TRST_N */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBALERT# */ PAD_CFG_NC(GPP_C2),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0CLK */ PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0DATA */ PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* EC_IN_RW */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* GPIO1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* GPIO2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* GPIO3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* GPIO4 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* SKU_ID0 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* SKU_ID1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* SKU_ID2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* SKU_ID3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SDA */ PAD_CFG_NC(GPP_C18),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* SCREW_SPI_WP_STATUS */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- PLTRST, EDGE), /* HP_IRQ_GPIO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* OEM_ID1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* OEM_ID2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* OEM_ID3 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- PLTRST), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* MB_PCIE_SATA#_DET */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* DB_PCIE_SATA#_DET */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */</span><br><span style="color: hsl(0, 100%, 40%);">-/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* Rear Dual-Stack USB Ports */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* Front USB Ports */</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* Rear Single USB Port */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* INT_HDMI_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* DDI2_HPD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* HDMI_DDCCLK_SW */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* HDMI_DDCCLK_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_I2C2_H1_3V3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_I2C2_H1_3V3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C4_SCL */ PAD_CFG_NC(GPP_F9),</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_I2C2_AUDIO_1V8_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">-/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_I2C2_AUDIO_1V8_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),</span><br><span style="color: hsl(0, 100%, 40%);">-/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */</span><br><span style="color: hsl(0, 100%, 40%);">-/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* RSVD */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(0, 100%, 40%);">-/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* LANPHYC */ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Early pad configuration in bootblock */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- PLTRST), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">-/* Ensure UART pins are in native mode for H1. */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(0, 100%, 40%);">-/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,</span><br><span style="color: hsl(0, 100%, 40%);">- DEEP), /* SCREW_SPI_WP_STATUS */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,</span><br><span style="color: hsl(0, 100%, 40%);">- NF1), /* MB_PCIE_SATA#_DET */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* __ACPI__ */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif /* BASEBOARD_GPIO_H */</span><br><span>diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h</span><br><span>new file mode 100644</span><br><span>index 0000000..41e0da0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __BASEBOARD_VARIANTS_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the board id for the current variant board. */</span><br><span style="color: hsl(120, 100%, 40%);">+uint8_t variant_board_id(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The next set of functions return the gpio table and fill in the number of</span><br><span style="color: hsl(120, 100%, 40%);">+ * entries for each table.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __BASEBOARD_VARIANTS_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28963">change 28963</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28963"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314 </div>
<div style="display:none"> Gerrit-Change-Number: 28963 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: David Wu <david_wu@quanta.corp-partner.google.com> </div>