<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28957">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)"<br><br>Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/apple/macbook21/romstage.c<br>M src/mainboard/apple/macbookair4_2/early_southbridge.c<br>M src/mainboard/asrock/g41c-gs/romstage.c<br>M src/mainboard/asus/p5gc-mx/romstage.c<br>M src/mainboard/foxconn/d41s/romstage.c<br>M src/mainboard/getac/p470/romstage.c<br>M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c<br>M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c<br>M src/mainboard/google/stout/chromeos.c<br>M src/mainboard/ibase/mb899/romstage.c<br>M src/mainboard/intel/d510mo/romstage.c<br>M src/mainboard/intel/d945gclf/romstage.c<br>M src/mainboard/intel/dcp847ske/early_southbridge.c<br>M src/mainboard/kontron/986lcd-m/romstage.c<br>M src/mainboard/lenovo/l520/romstage.c<br>M src/mainboard/lenovo/s230u/romstage.c<br>M src/mainboard/lenovo/t60/romstage.c<br>M src/mainboard/lenovo/x201/romstage.c<br>M src/mainboard/lenovo/x60/romstage.c<br>M src/mainboard/lenovo/z61t/romstage.c<br>M src/mainboard/packardbell/ms2290/romstage.c<br>M src/mainboard/packardbell/ms2290/smihandler.c<br>M src/mainboard/roda/rk886ex/romstage.c<br>M src/mainboard/sapphire/pureplatinumh61/romstage.c<br>24 files changed, 200 insertions(+), 164 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28957/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c</span><br><span>index ee322ae..3d76f56 100644</span><br><span>--- a/src/mainboard/apple/macbook21/romstage.c</span><br><span>+++ b/src/mainboard/apple/macbook21/romstage.c</span><br><span>@@ -33,10 +33,12 @@</span><br><span> #include <northbridge/intel/i945/raminit.h></span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> /* Enable Serial IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> </span><br><span> /* I/O Decode Ranges</span><br><span> * X60: 0x0210 == 00000010 00010000</span><br><span>@@ -46,7 +48,7 @@</span><br><span> * 00 = 378h - 37Fh and 778h - 77Fh</span><br><span> * 10 = 3BCh - 3BEh and 7BCh - 7BEh</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span> </span><br><span> /* LPC_EN--LPC I/F Enables Register</span><br><span> * X60: 0x1f0d == 00011111 00001101</span><br><span>@@ -100,7 +102,7 @@</span><br><span> * interface. This range is selected in the LPC_COM Decode</span><br><span> * Range Register (D31:F0:80h, bits 3:2).</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN</span><br><span> | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN</span><br><span> | COMA_LPC_EN);</span><br><span> </span><br><span>@@ -126,19 +128,19 @@</span><br><span> * 1 = Enable the GEN1 I/O range to be forwarded to the LPC</span><br><span> * I/F</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0681);</span><br><span> </span><br><span> /* GEN2_DEC, LPC Interface Generic Decode Range 2</span><br><span> * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001</span><br><span> * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c1641);</span><br><span> </span><br><span> /* GEN4_DEC, LPC Interface Generic Decode Range 4</span><br><span> * X60: 0x0000 0x0000</span><br><span> * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN4_DEC, 0x001c0301);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span>@@ -188,14 +190,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> /* reset rtc power status */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> /* usb transient disconnect */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>index d189ae2..51fcb55 100644</span><br><span>--- a/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c</span><br><span>@@ -23,15 +23,17 @@</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <cbfs.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0x82, 0x3f0f);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x84, 0x000c0681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x88, 0x000c1641);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x8c, 0x001c0301);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x90, 0x00fc0701);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0x80, 0x0070);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0xac, 0x80000000);</span><br><span> }</span><br><span> </span><br><span> void mainboard_rcba_config(void)</span><br><span>diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c</span><br><span>index 90df5390..7c75bba 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/romstage.c</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/romstage.c</span><br><span>@@ -77,11 +77,11 @@</span><br><span> </span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> /* Decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN</span><br><span> | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0291);</span><br><span> }</span><br><span> </span><br><span> void mainboard_romstage_entry(unsigned long bist)</span><br><span>diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>index dacc396..783df6b 100644</span><br><span>--- a/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>+++ b/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #include <cpu/intel/speedstep.h></span><br><span> #include <arch/cpu.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)</span><br><span> #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)</span><br><span> </span><br><span>@@ -105,15 +106,15 @@</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // Set COM1/COM2 decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span> // Enable COM1</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN</span><br><span> | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN</span><br><span> | COMA_LPC_EN);</span><br><span> // Enable SuperIO Power Management Events</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x00040291);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span>@@ -138,14 +139,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c</span><br><span>index 3f81e67..871a331 100644</span><br><span>--- a/src/mainboard/foxconn/d41s/romstage.c</span><br><span>+++ b/src/mainboard/foxconn/d41s/romstage.c</span><br><span>@@ -36,6 +36,7 @@</span><br><span> #include <romstage_handoff.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)</span><br><span> </span><br><span> /* Early mainboard specific GPIO setup */</span><br><span>@@ -56,16 +57,16 @@</span><br><span> static void nm10_enable_lpc(void)</span><br><span> {</span><br><span> /* Disable Serial IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> /* Decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config16(LPC_DEV, LPC_IO_DEC) | 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN</span><br><span> | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN</span><br><span> | COMA_LPC_EN);</span><br><span> </span><br><span> /* Environment Controller */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span>diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c</span><br><span>index 7498247..71f2df1 100644</span><br><span>--- a/src/mainboard/getac/p470/romstage.c</span><br><span>+++ b/src/mainboard/getac/p470/romstage.c</span><br><span>@@ -33,6 +33,8 @@</span><br><span> #include <timestamp.h></span><br><span> #include "option_table.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void setup_special_ich7_gpios(void)</span><br><span> {</span><br><span> u32 gpios;</span><br><span>@@ -60,19 +62,19 @@</span><br><span> lpt_en = LPT_LPC_EN;</span><br><span> </span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0007);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN</span><br><span> | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN</span><br><span> | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);</span><br><span> // Enable 0x02e0 - 0x2ff</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x001c02e1);</span><br><span> // Enable 0x600 - 0x6ff</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x00fc0601);</span><br><span> // Enable 0x68 - 0x6f</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN3_DEC, 0x00040069);</span><br><span> }</span><br><span> </span><br><span> /* This box has two superios, so enabling serial becomes slightly excessive.</span><br><span>@@ -192,14 +194,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>index 49a25af..4790e9e 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>@@ -34,6 +34,7 @@</span><br><span> #include <northbridge/intel/i945/raminit.h></span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)</span><br><span> #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)</span><br><span> #define EC_DEV PNP_DEV(0x2e, IT8718F_EC)</span><br><span>@@ -66,17 +67,17 @@</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // Set COM1/COM2 decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0000);</span><br><span> // Enable COM1</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN</span><br><span> | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN</span><br><span> | COMA_LPC_EN);</span><br><span> // Enable SuperIO Power Management Events</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0801);</span><br><span> /* LPC decode range 2: Environment Controller */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x00040291);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span>@@ -100,14 +101,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c</span><br><span>index 13c888e..997c74b 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include <northbridge/intel/x4x/iomap.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)</span><br><span> #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)</span><br><span> #define EC_DEV PNP_DEV(0x2e, IT8718F_EC)</span><br><span>@@ -118,14 +119,14 @@</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> /* Disable Serial IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0x00);</span><br><span> /* Decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN,</span><br><span> CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN</span><br><span> | LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x007c0291);</span><br><span> }</span><br><span> </span><br><span> void mainboard_romstage_entry(unsigned long bist)</span><br><span>diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c</span><br><span>index 6d77a2a..d9e9b59 100644</span><br><span>--- a/src/mainboard/google/stout/chromeos.c</span><br><span>+++ b/src/mainboard/google/stout/chromeos.c</span><br><span>@@ -26,6 +26,8 @@</span><br><span> #include "ec.h"</span><br><span> #include <ec/quanta/it8518/ec.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #ifndef __PRE_RAM__</span><br><span> #include <boot/coreboot_tables.h></span><br><span> </span><br><span>@@ -97,7 +99,7 @@</span><br><span> int get_recovery_mode_switch(void)</span><br><span> {</span><br><span> #ifdef __PRE_RAM__</span><br><span style="color: hsl(0, 100%, 40%);">- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = LPC_DEV;</span><br><span> #else</span><br><span> static int ec_in_rec_mode = 0;</span><br><span> static int ec_rec_flag_good = 0;</span><br><span>diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c</span><br><span>index 78ec5ed..84dc356 100644</span><br><span>--- a/src/mainboard/ibase/mb899/romstage.c</span><br><span>+++ b/src/mainboard/ibase/mb899/romstage.c</span><br><span>@@ -31,23 +31,24 @@</span><br><span> #include <superio/winbond/common/winbond.h></span><br><span> #include <superio/winbond/w83627ehg/w83627ehg.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)</span><br><span> #define SUPERIO_DEV PNP_DEV(0x4e, 0)</span><br><span> </span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // Set COM1/COM2 decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span> // Enable COM1/COM2/KBD/SuperIO1+2</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN</span><br><span> | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN</span><br><span> | COMB_LPC_EN);</span><br><span> // Enable HWM at 0x290</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0291);</span><br><span> // io 0x300 decode</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN4_DEC, 0x00000301);</span><br><span> }</span><br><span> </span><br><span> /* This box has one superio</span><br><span>@@ -155,14 +156,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c</span><br><span>index 77384ee..00c5cb8 100644</span><br><span>--- a/src/mainboard/intel/d510mo/romstage.c</span><br><span>+++ b/src/mainboard/intel/d510mo/romstage.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> #include <romstage_handoff.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)</span><br><span> #define SUPERIO_DEV PNP_DEV(0x4e, 0)</span><br><span> </span><br><span>@@ -57,15 +58,15 @@</span><br><span> static void nm10_enable_lpc(void)</span><br><span> {</span><br><span> /* Disable Serial IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0x00);</span><br><span> /* Decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,</span><br><span style="color: hsl(0, 100%, 40%);">- pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config16(LPC_DEV, LPC_IO_DEC) | 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN</span><br><span> | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN</span><br><span> | COMB_LPC_EN);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x7c0291);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span>diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>index 57f32c2..9f09391 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/romstage.c</span><br><span>+++ b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>@@ -29,20 +29,21 @@</span><br><span> #include <northbridge/intel/i945/raminit.h></span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)</span><br><span> #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)</span><br><span> </span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // Set COM1/COM2 decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span> // Enable COM1</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN</span><br><span> | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);</span><br><span> // Enable SuperIO Power Management Events</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c0681);</span><br><span> }</span><br><span> </span><br><span> static void rcba_config(void)</span><br><span>@@ -80,14 +81,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>index c4be4d50..5c18135 100644</span><br><span>--- a/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c</span><br><span>@@ -33,12 +33,14 @@</span><br><span> #define DEBUG_UART_EN COMA_LPC_EN</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN,</span><br><span> CNF2_LPC_EN | DEBUG_UART_EN);</span><br><span> /* Decode SuperIO 0x0a00 */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x00fc0a01);</span><br><span> }</span><br><span> </span><br><span> void mainboard_rcba_config(void)</span><br><span>diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>index 467606a..6b0ec5b 100644</span><br><span>--- a/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>+++ b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>@@ -33,6 +33,7 @@</span><br><span> </span><br><span> #include "option_table.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)</span><br><span> </span><br><span> static void ich7_enable_lpc(void)</span><br><span>@@ -42,21 +43,21 @@</span><br><span> lpt_en = LPT_LPC_EN; /* enable LPT */</span><br><span> </span><br><span> /* Enable Serial IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> /* Set COM1/COM2 decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span> /* Enable COM1/COM2/KBD/SuperIO1+2 */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN</span><br><span> | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN</span><br><span> | COMB_LPC_EN | lpt_en);</span><br><span> /* Enable HWM at 0xa00 */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);</span><br><span> /* COM3 decode */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x000403e9);</span><br><span> /* COM4 decode */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN3_DEC, 0x000402e9);</span><br><span> /* io 0x300 decode */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN4_DEC, 0x00000301);</span><br><span> }</span><br><span> </span><br><span> /* This box has two superios, so enabling serial becomes slightly excessive.</span><br><span>@@ -245,14 +246,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> /* reset rtc power status */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> /* usb transient disconnect */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c</span><br><span>index 0f6ffed..cd0bb08 100644</span><br><span>--- a/src/mainboard/lenovo/l520/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/l520/romstage.c</span><br><span>@@ -23,13 +23,15 @@</span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0x82, 0x3c0c);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x84, 0x007c1611);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x88, 0x00040069);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x8c, 0x000c0701);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x90, 0x00000000);</span><br><span> }</span><br><span> </span><br><span> void mainboard_rcba_config(void)</span><br><span>diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c</span><br><span>index 7e002d4..0e6df78 100644</span><br><span>--- a/src/mainboard/lenovo/s230u/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/s230u/romstage.c</span><br><span>@@ -28,22 +28,23 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include "ec.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> #define SPD_LEN 256</span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0x82, 0x0c00);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x84, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x88, 0x000c0701);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x8c, 0x000c0069);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x90, 0x000c06a1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, ETR3, 0x10000);</span><br><span> </span><br><span> /* Memory map KB9012 EC registers */</span><br><span> pci_write_config32(</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEV(0, 0x1f, 0), 0x98,</span><br><span style="color: hsl(120, 100%, 40%);">+ LPC_DEV, 0x98,</span><br><span> CONFIG_EC_BASE_ADDRESS | 1);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0xd8, 0xffc0);</span><br><span> </span><br><span> /* Enable external USB port power. */</span><br><span> if (IS_ENABLED(CONFIG_USBDEBUG))</span><br><span>diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c</span><br><span>index e4a8efb..a52ea6d 100644</span><br><span>--- a/src/mainboard/lenovo/t60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t60/romstage.c</span><br><span>@@ -36,25 +36,27 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include "dock.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN</span><br><span> | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN</span><br><span> | LPT_LPC_EN | COMA_LPC_EN);</span><br><span> </span><br><span> /* range 0x1600 - 0x167f */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601);</span><br><span> </span><br><span> /* range 0x15e0 - 0x15ef */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1);</span><br><span> </span><br><span> /* range 0x1680 - 0x169f */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681);</span><br><span> }</span><br><span> </span><br><span> static void early_superio_config(void)</span><br><span>@@ -120,14 +122,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>@@ -181,9 +183,9 @@</span><br><span> ich7_enable_lpc();</span><br><span> </span><br><span> /* We want early GPIO setup, to be able to detect legacy I/O module */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1);</span><br><span> /* Enable GPIOs */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0x4c /* GC */, 0x10);</span><br><span> setup_pch_gpios(&mainboard_gpio_map);</span><br><span> </span><br><span> dock_err = dlpc_init();</span><br><span>diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c</span><br><span>index d241422..66dee90 100644</span><br><span>--- a/src/mainboard/lenovo/x201/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x201/romstage.c</span><br><span>@@ -43,6 +43,8 @@</span><br><span> #include <northbridge/intel/nehalem/raminit.h></span><br><span> #include <southbridge/intel/ibexpeak/me.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void pch_enable_lpc(void)</span><br><span> {</span><br><span> /* X201 EC Decode Range Port60/64, Port62/66 */</span><br><span>@@ -215,7 +217,7 @@</span><br><span> printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);</span><br><span> if (((reg32 >> 10) & 7) == 5) {</span><br><span> u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa2);</span><br><span> printk(BIOS_DEBUG, "a2: %02x\n", reg8);</span><br><span> if (!(reg8 & 0x20)) {</span><br><span> outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);</span><br><span>diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c</span><br><span>index 81ee5da..9b86b4f 100644</span><br><span>--- a/src/mainboard/lenovo/x60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x60/romstage.c</span><br><span>@@ -36,24 +36,26 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include "dock.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN</span><br><span> | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN</span><br><span> | LPT_LPC_EN | COMA_LPC_EN);</span><br><span> /* range 0x1600 - 0x167f */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601);</span><br><span> </span><br><span> /* range 0x15e0 - 0x15ef */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1);</span><br><span> </span><br><span> /* range 0x1680 - 0x169f */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681);</span><br><span> }</span><br><span> </span><br><span> static void early_superio_config(void)</span><br><span>@@ -119,14 +121,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>@@ -177,8 +179,8 @@</span><br><span> enable_lapic();</span><br><span> </span><br><span> /* Enable GPIOs */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0x4c, 0x10); /* 0x4c == GC */</span><br><span> setup_pch_gpios(&mainboard_gpio_map);</span><br><span> </span><br><span> ich7_enable_lpc();</span><br><span>diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c</span><br><span>index 94c8a8f..59afc7f 100644</span><br><span>--- a/src/mainboard/lenovo/z61t/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/z61t/romstage.c</span><br><span>@@ -36,25 +36,27 @@</span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include "dock.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> // Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210);</span><br><span> // decode range</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN</span><br><span> | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN</span><br><span> | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);</span><br><span> </span><br><span> /* range 0x1600 - 0x167f */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601);</span><br><span> </span><br><span> /* range 0x15e0 - 0x15ef */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1);</span><br><span> </span><br><span> /* range 0x1680 - 0x169f */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681);</span><br><span> }</span><br><span> </span><br><span> static void early_superio_config(void)</span><br><span>@@ -120,14 +122,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> // reset rtc power status</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> // usb transient disconnect</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>@@ -181,9 +183,9 @@</span><br><span> ich7_enable_lpc();</span><br><span> </span><br><span> /* We want early GPIO setup, to be able to detect legacy I/O module */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1);</span><br><span> /* Enable GPIOs */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0x4c /* GC */, 0x10);</span><br><span> setup_pch_gpios(&mainboard_gpio_map);</span><br><span> </span><br><span> dock_err = dlpc_init();</span><br><span>diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c</span><br><span>index adb0cec..2507c8b 100644</span><br><span>--- a/src/mainboard/packardbell/ms2290/romstage.c</span><br><span>+++ b/src/mainboard/packardbell/ms2290/romstage.c</span><br><span>@@ -41,6 +41,8 @@</span><br><span> #include <northbridge/intel/nehalem/raminit.h></span><br><span> #include <southbridge/intel/ibexpeak/me.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV LPC_DEV</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void pch_enable_lpc(void)</span><br><span> {</span><br><span> /* Enable EC, PS/2 Keyboard/Mouse */</span><br><span>@@ -214,7 +216,7 @@</span><br><span> printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);</span><br><span> if (((reg32 >> 10) & 7) == 5) {</span><br><span> u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa2);</span><br><span> printk(BIOS_DEBUG, "a2: %02x\n", reg8);</span><br><span> if (!(reg8 & 0x20)) {</span><br><span> outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);</span><br><span>diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>index 926650a..7b3e9d6 100644</span><br><span>--- a/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>+++ b/src/mainboard/packardbell/ms2290/smihandler.c</span><br><span>@@ -24,6 +24,8 @@</span><br><span> #include <ec/acpi/ec.h></span><br><span> #include <delay.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void mainboard_smm_init(void)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "initializing SMI\n");</span><br><span>@@ -74,16 +76,16 @@</span><br><span> mainboard_finalized = 1;</span><br><span> break;</span><br><span> case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pci_read_config8(LPC_DEV, 0xbb);</span><br><span> tmp &= ~0x03;</span><br><span> tmp |= 0x02;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xbb, tmp);</span><br><span> break;</span><br><span> case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pci_read_config8(LPC_DEV, 0xbb);</span><br><span> tmp &= ~0x03;</span><br><span> tmp |= 0x01;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xbb, tmp);</span><br><span> break;</span><br><span> default:</span><br><span> break;</span><br><span>diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c</span><br><span>index 7f233e8..b921382 100644</span><br><span>--- a/src/mainboard/roda/rk886ex/romstage.c</span><br><span>+++ b/src/mainboard/roda/rk886ex/romstage.c</span><br><span>@@ -35,6 +35,8 @@</span><br><span> #include <southbridge/intel/i82801gx/i82801gx.h></span><br><span> #include "option_table.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void ich7_enable_lpc(void)</span><br><span> {</span><br><span> int lpt_en = 0;</span><br><span>@@ -42,19 +44,19 @@</span><br><span> lpt_en = LPT_LPC_EN; /* enable LPT */</span><br><span> </span><br><span> /* Enable Serial IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);</span><br><span> /* decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0007);</span><br><span> /* decode range */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN</span><br><span> | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN</span><br><span> | FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN);</span><br><span> /* COM3 and COM4 decode? */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN1_DEC, 0x1c02e1);</span><br><span> /* ??decode?? */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN2_DEC, 0x00fc0601);</span><br><span> /* EC decode? */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, GEN3_DEC, 0x00040069);</span><br><span> }</span><br><span> </span><br><span> /* This box has two superios, so enabling serial becomes slightly excessive.</span><br><span>@@ -158,14 +160,14 @@</span><br><span> pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);</span><br><span> </span><br><span> /* reset rtc power status */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xa4);</span><br><span> reg8 &= ~(1 << 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xa4, reg8);</span><br><span> </span><br><span> /* usb transient disconnect */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(LPC_DEV, 0xad);</span><br><span> reg8 |= (3 << 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, 0xad, reg8);</span><br><span> </span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);</span><br><span> reg32 |= (1 << 29) | (1 << 17);</span><br><span>diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>index da825a9..cdc5993 100644</span><br><span>--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c</span><br><span>@@ -25,16 +25,17 @@</span><br><span> #include <northbridge/intel/sandybridge/raminit_native.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0x82, 0x2400);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x84, 0x000c0291);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x88, 0x000c0a01);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x8c, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0x90, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, 0x80, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, 0xac, 0x00010000);</span><br><span> }</span><br><span> </span><br><span> void mainboard_rcba_config(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28957">change 28957</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28957"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695 </div>
<div style="display:none"> Gerrit-Change-Number: 28957 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>