<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28932">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS<br><br>The logic for setting the PCIEXPWAK_STS is backwards.  According<br>to EDS, PCIEXPWAK_STS should be set to disable "the inputs to<br>the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the<br>system", but the logic was setting that bit if DSX_EN_WAKE_PIN is<br>enabled, not disabled.  This was causing spurious wake issues on<br>nocturne.<br><br>Changed logic to set the PCIEXPWAK_STS bit if DSX_EN_WAKE_PIN is<br>not defined in deep_sx_config register in devicetree.cb.<br><br>BUG=b:111683988<br>TEST="emerge-nocturne coreboot chromeos-bootimage', flash build<br>onto nocturne, boot nocturne, and verify that pulling WAKE# pin<br>low does not wake the system.<br><br>Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>M src/soc/intel/skylake/acpi.c<br>1 file changed, 1 insertion(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28932/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c</span><br><span>index d2ec7e7..bc3ea45 100644</span><br><span>--- a/src/soc/intel/skylake/acpi.c</span><br><span>+++ b/src/soc/intel/skylake/acpi.c</span><br><span>@@ -715,7 +715,7 @@</span><br><span>             pm1_en |= PWRBTN_STS; /* Always enabled as wake source */</span><br><span>            if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)</span><br><span>                     gpe0_std |= LAN_WAK_EN;</span><br><span style="color: hsl(0, 100%, 40%);">-         if (config->deep_sx_config & DSX_EN_WAKE_PIN)</span><br><span style="color: hsl(120, 100%, 40%);">+          if ((config->deep_sx_config & DSX_EN_WAKE_PIN) == 0)</span><br><span>                  pm1_en |= PCIEXPWAK_STS;</span><br><span>     }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28932">change 28932</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28932"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da </div>
<div style="display:none"> Gerrit-Change-Number: 28932 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>