<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28939">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled<br><br>This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not<br>enabled on the platform. This is required to prevent unnecessary wakes<br>if the WAKE# pin remains not connected on the platform.<br><br>BUG=b:117284700<br>TEST=Verified that no spurious wakes are observed on nocturne.<br><br>Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/soc/intel/skylake/cpu.c<br>1 file changed, 13 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28939/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 417c4bc..925b694 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -466,14 +466,26 @@</span><br><span> </span><br><span> static void post_mp_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+       struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+     config_t *conf;</span><br><span style="color: hsl(120, 100%, 40%);">+       uint16_t pm1_en = GBL_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  /* Set Max Ratio */</span><br><span>  cpu_set_max_ratio();</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+      if (dev && dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+               conf = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+             if (!(conf->deep_sx_config & DSX_EN_WAKE_PIN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+                       printk(BIOS_INFO, "Setting PCI Express Wake Disable.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+                   pm1_en |= PCIEXPWAK_DIS;</span><br><span style="color: hsl(120, 100%, 40%);">+              }</span><br><span style="color: hsl(120, 100%, 40%);">+     }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  /*</span><br><span>    * Now that all APs have been relocated as well as the BSP let SMIs</span><br><span>   * start flowing.</span><br><span>     */</span><br><span style="color: hsl(0, 100%, 40%);">-     smm_southbridge_enable(GBL_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+       smm_southbridge_enable(pm1_en);</span><br><span> </span><br><span>  /* Lock down the SMRAM space. */</span><br><span> #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28939">change 28939</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28939"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe </div>
<div style="display:none"> Gerrit-Change-Number: 28939 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>