<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28909">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address<br><br>Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/gm45/iommu.c<br>M src/northbridge/intel/i945/early_init.c<br>M src/northbridge/intel/pineview/gma.c<br>3 files changed, 3 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/28909/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c</span><br><span>index 0108116..3a93dc5 100644</span><br><span>--- a/src/northbridge/intel/gm45/iommu.c</span><br><span>+++ b/src/northbridge/intel/gm45/iommu.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span>   MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */</span><br><span> </span><br><span>    /* clear GTT */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);</span><br><span style="color: hsl(120, 100%, 40%);">+  u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC);</span><br><span>     if (gtt & 0x400) { /* VT mode */</span><br><span>                 pci_devfn_t igd = PCI_DEV(0, 2, 0);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c</span><br><span>index 7de2c73..a38874a 100644</span><br><span>--- a/src/northbridge/intel/i945/early_init.c</span><br><span>+++ b/src/northbridge/intel/i945/early_init.c</span><br><span>@@ -685,7 +685,7 @@</span><br><span>       if (reg32 == 0x030000) {</span><br><span>             printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");</span><br><span>                reg16 = (1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">-         pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+          pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16);</span><br><span> </span><br><span>              reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);</span><br><span>                reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);</span><br><span>diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c</span><br><span>index eb67c65..e075ac1 100644</span><br><span>--- a/src/northbridge/intel/pineview/gma.c</span><br><span>+++ b/src/northbridge/intel/pineview/gma.c</span><br><span>@@ -98,7 +98,7 @@</span><br><span> </span><br><span>        gtt_setup(mmio);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    pci_write_config16(vga, 0x52, 0x130);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(vga, GGC, 0x130);</span><br><span> </span><br><span>     /* Disable VGA.  */</span><br><span>  write32(mmio + VGACNTRL, VGA_DISP_DISABLE);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28909">change 28909</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28909"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e </div>
<div style="display:none"> Gerrit-Change-Number: 28909 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>