<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28890">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions.<br><br>-cnl PCH-H has 12 GPIO groups which are grouped under 5 gpio community.<br><br>-Add gpio pin definitions for CNP-H and related changes.<br><br>-Add gpio device name, host software owenership reg offset for CNP-H.<br><br>BUG: none<br>TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &<br> RVP11 and verified power management, IO device functionalities<br> works fine.<br><br>Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e<br>Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>---<br>M src/soc/intel/cannonlake/acpi/gpio.asl<br>M src/soc/intel/cannonlake/gpio.c<br>M src/soc/intel/cannonlake/include/soc/gpio.h<br>M src/soc/intel/cannonlake/include/soc/gpio_defs.h<br>M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>M src/soc/intel/cannonlake/include/soc/pmc.h<br>6 files changed, 545 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28890/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl</span><br><span>index 8a990b3..bcf67f9 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi/gpio.asl</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/gpio.asl</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -20,7 +20,11 @@</span><br><span> </span><br><span> Device (GPIO)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, "INT3450")</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> Name (_HID, "INT34BB")</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> Name (_UID, 0)</span><br><span> Name (_DDN, "GPIO Controller")</span><br><span> </span><br><span>@@ -83,6 +87,7 @@</span><br><span> */</span><br><span> Method (GADD, 1, NotSerialized)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span> /* GPIO Community 0 */</span><br><span> If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))</span><br><span> {</span><br><span>@@ -116,6 +121,35 @@</span><br><span> Store (PCRB (Local0), Local2)</span><br><span> Add (Local2, PAD_CFG_BASE, Local2)</span><br><span> Return (Add (Local2, Multiply (Local1, 16)))</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM0, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_A0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_C0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 3*/</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM3, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_K0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11)))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM4, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_I0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PCRB (Local0), Local2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (Local2, PAD_CFG_BASE, Local2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Add (Local2, Multiply (Local1, 16)))</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c</span><br><span>index 0befba0..ca3b7ec 100644</span><br><span>--- a/src/soc/intel/cannonlake/gpio.c</span><br><span>+++ b/src/soc/intel/cannonlake/gpio.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 - 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2018 Intel Corp.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -31,7 +31,7 @@</span><br><span> { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },</span><br><span> { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span> static const struct pad_group cnl_community0_groups[] = {</span><br><span> INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */</span><br><span> INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */</span><br><span>@@ -145,6 +145,118 @@</span><br><span> .num_groups = ARRAY_SIZE(cnl_community4_groups),</span><br><span> }</span><br><span> };</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group cnl_community0_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group cnl_community1_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group cnl_community2_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group cnl_community3_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K*/</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_group cnl_community4_groups[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_community cnl_communities[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { /* GPP A, B */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_A0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_B23,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_AB",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map_com0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map_com0),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = cnl_community0_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(cnl_community0_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP C, D, G */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_G7,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_CDG",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = cnl_community1_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(cnl_community1_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM2,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPD0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPD11,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPD",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = cnl_community2_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(cnl_community2_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP K, H, E, F */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM3,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_K0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_F23,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_KHEF",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = cnl_community3_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(cnl_community3_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP I, J */</span><br><span style="color: hsl(120, 100%, 40%);">+ .port = PID_GPIOCOM4,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_I0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_J11,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pad_cfg_base = PAD_CFG_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_IJ",</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_map = rst_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span style="color: hsl(120, 100%, 40%);">+ .groups = cnl_community4_groups,</span><br><span style="color: hsl(120, 100%, 40%);">+ .num_groups = ARRAY_SIZE(cnl_community4_groups),</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> const struct pad_community *soc_gpio_get_community(size_t *num_communities)</span><br><span> {</span><br><span>@@ -163,6 +275,11 @@</span><br><span> { PMC_GPP_F, GPP_F },</span><br><span> { PMC_GPP_G, GPP_G },</span><br><span> { PMC_GPP_H, GPP_H },</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_I, GPP_I },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_J, GPP_J },</span><br><span style="color: hsl(120, 100%, 40%);">+ { PMC_GPP_K, GPP_K },</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> { PMC_GPD, GPD },</span><br><span> };</span><br><span> *num = ARRAY_SIZE(routes);</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h</span><br><span>index 2d9f3d7..a2b6f5e 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/gpio.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/gpio.h</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -18,7 +18,10 @@</span><br><span> </span><br><span> #include <soc/gpio_defs.h></span><br><span> #include <intelblocks/gpio.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CROS_GPIO_DEVICE_NAME "INT3450:00"</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #define CROS_GPIO_DEVICE_NAME "INT34BB:00"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h</span><br><span>index 716f59d..6f9c03a 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-2018 Intel Corp.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -240,12 +240,92 @@</span><br><span> #define GPP_H21_IRQ 0x5d</span><br><span> #define GPP_H22_IRQ 0x5e</span><br><span> #define GPP_H23_IRQ 0x5f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group I */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I0_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I1_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I2_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I3_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I4_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I5_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I6_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I7_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I8_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I9_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I10_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I11_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I12_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I13_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I14_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I15_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I16_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I17_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I18_IRQ 0x2a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I19_IRQ 0x2b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I20_IRQ 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I21_IRQ 0x2d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I22_IRQ 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I23_IRQ 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group J */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J0_IRQ 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J1_IRQ 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J2_IRQ 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J3_IRQ 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J4_IRQ 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J5_IRQ 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J6_IRQ 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J7_IRQ 0x37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J8_IRQ 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J9_IRQ 0x39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J10_IRQ 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J11_IRQ 0x3b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J12_IRQ 0x3c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J13_IRQ 0x3d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J14_IRQ 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J15_IRQ 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J16_IRQ 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J17_IRQ 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J18_IRQ 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J19_IRQ 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J20_IRQ 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J21_IRQ 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J22_IRQ 0x46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J23_IRQ 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group K */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K0_IRQ 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K1_IRQ 0x49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K2_IRQ 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K3_IRQ 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K4_IRQ 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K5_IRQ 0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K6_IRQ 0x4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K7_IRQ 0x4f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K8_IRQ 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K9_IRQ 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K10_IRQ 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K11_IRQ 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K12_IRQ 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K13_IRQ 0x55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K14_IRQ 0x56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K15_IRQ 0x57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K16_IRQ 0x58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K17_IRQ 0x59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K18_IRQ 0x5a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K19_IRQ 0x5b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K20_IRQ 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K21_IRQ 0x5d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K22_IRQ 0x5e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K23_IRQ 0x5f</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> /* Register defines. */</span><br><span> #define GPIO_MISCCFG 0x10</span><br><span> #define GPE_DW_SHIFT 8</span><br><span> #define GPE_DW_MASK 0xfff00</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOSTSW_OWN_REG_0 0xc0</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #define HOSTSW_OWN_REG_0 0xb0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #define GPI_SMI_STS_0 0x180</span><br><span> #define GPI_SMI_EN_0 0x1A0</span><br><span> #define PAD_CFG_BASE 0x600</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h</span><br><span>index a1ce8c4..db6ce57 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright 2015 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-2018 Intel Corp.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -22,6 +22,7 @@</span><br><span> * The GPIO groups are accessed through register blocks called</span><br><span> * communities.</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+#if !IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span> #define GPP_A 0</span><br><span> #define GPP_B 1</span><br><span> #define GPP_G 2</span><br><span>@@ -352,4 +353,290 @@</span><br><span> #define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)</span><br><span> </span><br><span> #define TOTAL_PADS 275</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD 0xC</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NUM_GROUPS 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MAX_NUM_PER_GROUP 24</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group A */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A1 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A2 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A3 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A4 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A5 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A6 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A7 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A8 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A9 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A10 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A11 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A12 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A13 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A14 14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A15 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A16 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A17 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A18 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A19 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A20 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A21 21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A22 22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_A23 23</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group B */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5 29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7 31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9 33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11 35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13 37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16 40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19 43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22 46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23 47</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM0_PADS (GPP_B23 - GPP_A0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group C */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3 51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5 53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6 54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8 56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9 57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10 58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12 60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13 61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14 62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15 63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18 66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21 69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23 71</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group D */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1 73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2 74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3 75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4 76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6 78</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9 81</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10 82</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11 83</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12 84</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14 86</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15 87</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16 88</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17 89</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19 91</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D20 92</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D21 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D22 94</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D23 95</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group G */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0 96</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1 97</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2 98</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3 99</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4 100</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5 101</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6 102</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7 103</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM1_PADS (GPP_G7 - GPP_C0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group K */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K0 104</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K1 105</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K2 106</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K3 107</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K4 108</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K5 109</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K6 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K7 111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K8 112</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K9 113</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K10 114</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K11 115</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K12 116</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K13 117</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K14 118</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K15 119</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K16 120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K17 121</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K18 122</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K19 123</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K20 124</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K21 125</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K22 126</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K23 127</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group H */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0 128</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1 129</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2 130</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3 131</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4 132</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5 133</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6 134</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7 135</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8 136</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9 137</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10 138</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11 139</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12 140</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13 141</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14 142</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15 143</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16 144</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17 145</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18 146</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19 147</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20 148</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21 149</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22 150</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23 151</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group E */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0 152</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1 153</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2 154</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3 155</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4 156</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5 157</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6 158</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7 159</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8 160</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9 161</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10 162</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11 163</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12 164</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group F */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0 165</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1 166</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2 167</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3 168</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4 169</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5 170</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6 171</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7 172</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8 173</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9 174</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10 175</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11 176</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12 177</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13 178</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14 179</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15 180</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16 181</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17 182</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18 183</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19 184</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F20 185</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F21 186</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F22 187</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F23 188</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM3_PADS (GPP_F23 - GPP_K0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group I */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I0 189</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I1 190</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I2 191</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I3 192</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I4 193</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I5 194</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I6 195</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I7 196</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I8 197</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I9 198</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I10 199</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I11 200</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I12 201</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I13 202</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I14 203</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group J */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J0 204</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J1 205</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J2 206</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J3 207</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J4 208</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J5 209</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J6 210</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J7 211</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J8 212</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J9 213</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J10 214</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J11 215</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group GPD */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0 216</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1 217</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2 218</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3 219</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4 220</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5 221</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6 222</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7 223</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8 224</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9 225</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10 226</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11 227</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOTAL_PADS (GPD11 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>index 90cd370..faa36d4 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -116,6 +116,20 @@</span><br><span> #define GPE0_DWX_MASK 0xf</span><br><span> #define GPE0_DW_SHIFT(x) (4*(x))</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_A 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_B 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_C 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_D 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_E 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_F 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_G 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_H 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_I 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_J 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPP_K 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_GPD 0xC</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #define PMC_GPP_A 0x0</span><br><span> #define PMC_GPP_B 0x1</span><br><span> #define PMC_GPP_C 0xD</span><br><span>@@ -125,6 +139,7 @@</span><br><span> #define PMC_GPP_G 0x2</span><br><span> #define PMC_GPP_H 0x6</span><br><span> #define PMC_GPD 0xA</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> #define GBLRST_CAUSE0 0x1924</span><br><span> #define GBLRST_CAUSE0_THERMTRIP (1 << 5)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28890">change 28890</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28890"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e </div>
<div style="display:none"> Gerrit-Change-Number: 28890 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>