<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28874">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/mainboard: Add emulation/spike-riscv.md<br><br>Move the usage instructions from their ad-hoc place in Kconfig.name to<br>the Documentation directory, and expand them a bit.<br><br>Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>A Documentation/mainboard/emulation/spike-riscv.md<br>M Documentation/mainboard/index.md<br>M src/mainboard/emulation/spike-riscv/Kconfig.name<br>3 files changed, 29 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28874/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md</span><br><span>new file mode 100644</span><br><span>index 0000000..55e87d9</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/emulation/spike-riscv.md</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Spike RISC-V emulator</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Installation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/></span><br><span style="color: hsl(120, 100%, 40%);">+- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>,</span><br><span style="color: hsl(120, 100%, 40%);">+ which are necessary in order to have a serial console</span><br><span style="color: hsl(120, 100%, 40%);">+- Compile `riscv-fesvr` and then `riscv-isa-sim`</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Building coreboot and running it in Spike</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- Configure coreboot and run `make` as usual</span><br><span style="color: hsl(120, 100%, 40%);">+- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to</span><br><span style="color: hsl(120, 100%, 40%);">+ convert coreboot to an ELF that Spike can load</span><br><span style="color: hsl(120, 100%, 40%);">+- Run `spike -m1024 build/coreboot.elf`</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[Spike]: https://github.com/riscv/riscv-isa-sim</span><br><span style="color: hsl(120, 100%, 40%);">+[RISC-V]: https://riscv.org/</span><br><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index c346a3b..c1e5262 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -10,6 +10,12 @@</span><br><span> </span><br><span> - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+## Emulation</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The boards in this section are not real mainboards, but emulators.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [Spike RISC-V emulator](emulation/spike-riscv.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ## Foxconn</span><br><span> </span><br><span> - [D41S](foxconn/d41s.md)</span><br><span>diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name</span><br><span>index 2869425..36dd509 100644</span><br><span>--- a/src/mainboard/emulation/spike-riscv/Kconfig.name</span><br><span>+++ b/src/mainboard/emulation/spike-riscv/Kconfig.name</span><br><span>@@ -1,7 +1,2 @@</span><br><span> config BOARD_EMULATION_SPIKE_UCB_RISCV</span><br><span> bool "SPIKE ucb riscv"</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- To run coreboot in spike:</span><br><span style="color: hsl(0, 100%, 40%);">- * run "make" as usual</span><br><span style="color: hsl(0, 100%, 40%);">- * util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}</span><br><span style="color: hsl(0, 100%, 40%);">- * spike -m1024 build/coreboot.elf</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28874">change 28874</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 </div>
<div style="display:none"> Gerrit-Change-Number: 28874 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>