<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28867">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variant/nocturne: set GPP_C19 to NF1<br><br>GPP_C19 was not being set as the code was incorrectly setting<br>GPP_C16 instead, so this change sets C19 to NF1.<br><br>Initialize GPP_E3 to a no connect.<br><br>BUG=b:117124878<br>TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and<br>verify that i2c transactions work for the left SAR sensor.<br><br>Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>M src/mainboard/google/poppy/variants/nocturne/gpio.c<br>1 file changed, 3 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28867/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>index 15a97c3..7724bc3 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>@@ -151,7 +151,7 @@</span><br><span>        /* C18 : I2C1_SDA ==> PCH_I2C1_DISPLAY_SAR_SDA */</span><br><span>         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),</span><br><span>        /* C19 : I2C1_SCL ==> PCH_I2C1_DISPLAY_SAR_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">-    PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),</span><br><span>        /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */</span><br><span>      PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span>        /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */</span><br><span>@@ -217,6 +217,8 @@</span><br><span>        /* E2  : SATAXPCIE2 ==> BT_DISABLE_L */</span><br><span>   PAD_CFG_GPO(GPP_E2, 1, DEEP),</span><br><span>        /* E3  : CPU_GP0 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(120, 100%, 40%);">+   /* E3  : DEVSLP0 ==> NC */</span><br><span>        PAD_CFG_NC(GPP_E4),</span><br><span>  /* E5  : SATA_DEVSLP1 ==> NC */</span><br><span>   PAD_CFG_NC(GPP_E5),</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28867">change 28867</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28867"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb </div>
<div style="display:none"> Gerrit-Change-Number: 28867 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>