<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28864">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Remove unused registers from ASL<br><br>Remove AcpiMmio and PCI config registers that are not used.<br><br>TEST=build Grunt<br>BUG=b:77602074<br><br>Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl<br>1 file changed, 0 insertions(+), 71 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28864/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl</span><br><span>index 7ac9139..a639260 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl</span><br><span>@@ -309,12 +309,6 @@</span><br><span> , 4,</span><br><span> U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */</span><br><span> SDSR, 1, /* SD 24 Shadow Reg Request Status Register */</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e88),</span><br><span style="color: hsl(0, 100%, 40%);">- SRSA, 32, /* Shadow Reg SRAM Addr */</span><br><span style="color: hsl(0, 100%, 40%);">- SRSD, 32, /* Shadow Reg SRAM DATA */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e94),</span><br><span style="color: hsl(0, 100%, 40%);">- SRDY, 1, /* S0i3 bios ready */</span><br><span> </span><br><span> offset (0x1ea0),</span><br><span> PG1A, 1,</span><br><span>@@ -341,40 +335,6 @@</span><br><span> Offset(0x00080054),</span><br><span> U_PS, 2,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* SATA */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00088010),</span><br><span style="color: hsl(0, 100%, 40%);">- ST10, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- ST14, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- ST18, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- ST1C, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- ST20, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- ST24, 32,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x0008802c),</span><br><span style="color: hsl(0, 100%, 40%);">- ST2C, 32,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00088040),</span><br><span style="color: hsl(0, 100%, 40%);">- ST40, 1,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00088044),</span><br><span style="color: hsl(0, 100%, 40%);">- ST44, 1,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x0008804c),</span><br><span style="color: hsl(0, 100%, 40%);">- , 2,</span><br><span style="color: hsl(0, 100%, 40%);">- DDIC, 1, /* DisableDynamicInterfaceClockPowerSaving */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00088064),</span><br><span style="color: hsl(0, 100%, 40%);">- S_PS, 2,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00088084),</span><br><span style="color: hsl(0, 100%, 40%);">- , 1,</span><br><span style="color: hsl(0, 100%, 40%);">- ST84, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- , 28,</span><br><span style="color: hsl(0, 100%, 40%);">- DSDN, 1, /* DShutDowN */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x0008808c),</span><br><span style="color: hsl(0, 100%, 40%);">- ST8C, 8,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* EHCI */</span><br><span> Offset(0x00090004),</span><br><span> , 1,</span><br><span>@@ -392,40 +352,9 @@</span><br><span> E_PS, 2,</span><br><span> </span><br><span> /* LPC Bridge */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a3078),</span><br><span style="color: hsl(0, 100%, 40%);">- , 2,</span><br><span style="color: hsl(0, 100%, 40%);">- LDQ0, 1,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> Offset(0x000a30cb),</span><br><span> , 7,</span><br><span> AUSS, 1, /* AutoSizeStart */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SD */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a7004),</span><br><span style="color: hsl(0, 100%, 40%);">- , 1,</span><br><span style="color: hsl(0, 100%, 40%);">- SDME, 1,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a7010),</span><br><span style="color: hsl(0, 100%, 40%);">- SDBA, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a702c),</span><br><span style="color: hsl(0, 100%, 40%);">- SD2C, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a7094),</span><br><span style="color: hsl(0, 100%, 40%);">- D_PS, 2,</span><br><span style="color: hsl(0, 100%, 40%);">- , 6,</span><br><span style="color: hsl(0, 100%, 40%);">- SDPE, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- , 6,</span><br><span style="color: hsl(0, 100%, 40%);">- PMES, 1,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a70b3), /* Version 2.0 = 0x1, Version 3.0 = 0x2 */</span><br><span style="color: hsl(0, 100%, 40%);">- SDB3, 8,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a70b4), /* Set Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- , 8,</span><br><span style="color: hsl(0, 100%, 40%);">- SETE, 1,</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a70d0),</span><br><span style="color: hsl(0, 100%, 40%);">- , 17,</span><br><span style="color: hsl(0, 100%, 40%);">- FC18, 1, /* Force 1.8v */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28864">change 28864</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa </div>
<div style="display:none"> Gerrit-Change-Number: 28864 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>