<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28853">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_PERF_{STATUS,CTL} to x86/msr.h<br><br>Change-Id: I7f884379bcaec8340031c914107a7277d620f448<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/cpu/via/nano/nano_init.c<br>M src/include/cpu/intel/speedstep.h<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/baytrail/include/soc/msr.h<br>M src/soc/intel/baytrail/tsc_freq.c<br>M src/soc/intel/braswell/include/soc/msr.h<br>M src/soc/intel/braswell/tsc_freq.c<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/common/block/cpu/cpulib.c<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/tsc_freq.c<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>19 files changed, 11 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28853/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index 7db870d..87f0525 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 953fdca..135a3f8 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 51a0deb..d1924cf 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -42,7 +42,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index 521e806..f26ac0f 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 9ab7466..606a65c 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c</span><br><span>index 62c6316..c8b054c 100644</span><br><span>--- a/src/cpu/via/nano/nano_init.c</span><br><span>+++ b/src/cpu/via/nano/nano_init.c</span><br><span>@@ -28,8 +28,6 @@</span><br><span> #define MODEL_NANO_3000_B0 0x8</span><br><span> #define MODEL_NANO_3000_B2 0xa</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_STATUS 0x00000198</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x00000199</span><br><span> #define MSR_IA32_MISC_ENABLE 0x000001a0</span><br><span> #define NANO_MYSTERIOUS_MSR 0x120e</span><br><span> </span><br><span>@@ -41,7 +39,7 @@</span><br><span> int cnt = 0;</span><br><span> do {</span><br><span> udelay(16);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_PERF_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_PERF_STATUS);</span><br><span> cnt++;</span><br><span> if (cnt > 128) {</span><br><span> printk(BIOS_WARNING,</span><br><span>@@ -61,7 +59,7 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> /* Get voltage and frequency info */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_PERF_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_PERF_STATUS);</span><br><span> u8 min_fid = (msr.hi >> 24);</span><br><span> u8 max_fid = (msr.hi >> 8) & 0xff;</span><br><span> u8 min_vid = (msr.hi >> 16) & 0xff;</span><br><span>@@ -78,7 +76,7 @@</span><br><span> /* Set highest frequency and VID */</span><br><span> msr.lo = msr.hi;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, msr);</span><br><span> /* Wait for the transition to complete, otherwise, the CPU</span><br><span> * might reset itself repeatedly */</span><br><span> nano_finish_fid_vid_transition();</span><br><span>diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h</span><br><span>index 05a61bb..d8b73f2 100644</span><br><span>--- a/src/include/cpu/intel/speedstep.h</span><br><span>+++ b/src/include/cpu/intel/speedstep.h</span><br><span>@@ -35,8 +35,6 @@</span><br><span> </span><br><span> </span><br><span> /* Speedstep related MSRs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_STATUS 0x198</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define MSR_THERM2_CTL 0x19D</span><br><span> #define IA32_MISC_ENABLES 0x1A0</span><br><span> #define MSR_EBC_FREQUENCY_ID 0x2c</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index f9d8f50..31449ed 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -22,6 +22,8 @@</span><br><span> #define CPUID_SMX (1 << 6)</span><br><span> #define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PERF_STATUS 0x198</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PERF_CTL 0x199</span><br><span> #define MSR_IA32_PAT 0x277</span><br><span> #define IA32_BIOS_UPDT_TRIG 0x79</span><br><span> #define IA32_BIOS_SIGN_ID 0x8b</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>index c207432b..fa0c40a 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>@@ -23,7 +23,6 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span> #define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span> #define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span>diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c</span><br><span>index 66fde22..0aee1d7 100644</span><br><span>--- a/src/soc/intel/baytrail/tsc_freq.c</span><br><span>+++ b/src/soc/intel/baytrail/tsc_freq.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* __SMM__ */</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>index 1ed6d3a..207a27d 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span> #define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span> #define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span>diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c</span><br><span>index b05a007..de82e23 100644</span><br><span>--- a/src/soc/intel/braswell/tsc_freq.c</span><br><span>+++ b/src/soc/intel/braswell/tsc_freq.c</span><br><span>@@ -91,7 +91,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* ENV_SMM */</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 13cc6f2..f26ec66 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -34,7 +34,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>index 112a049..ebbdabd 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>@@ -95,7 +95,7 @@</span><br><span> perf_ctl.lo = (msr.lo & 0xff) << 8;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>@@ -115,7 +115,7 @@</span><br><span> perf_ctl.lo = (msr.lo & 0xff) << 8;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>@@ -135,7 +135,7 @@</span><br><span> perf_ctl.lo = msr.lo & 0xff00;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index 15aac62..13276a6 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -45,7 +45,6 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> /* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */</span><br><span> #define BURST_MODE_DISABLE (1 << 6)</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index c816ea4..8a07865 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -36,7 +36,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>index c64810e..e6143ae 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span> #define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>index 66fde22..0aee1d7 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* __SMM__ */</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index d81ed85..f240722 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> </span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define IA32_MC0_CTL 0x400</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28853">change 28853</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7f884379bcaec8340031c914107a7277d620f448 </div>
<div style="display:none"> Gerrit-Change-Number: 28853 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>