<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28835">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add EMI init for DDR driver init<br><br>Add EMI config to initialize memory.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br> patches.<br><br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea<br>---<br>M src/soc/mediatek/mt8183/Makefile.inc<br>M src/soc/mediatek/mt8183/emi.c<br>A src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h<br>A src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h<br>M src/soc/mediatek/mt8183/include/soc/emi.h<br>A src/soc/mediatek/mt8183/memory.c<br>6 files changed, 505 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28835/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index 8fece79..3cd845d 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -21,6 +21,7 @@</span><br><span> verstage-y += ../common/wdt.c</span><br><span> </span><br><span> romstage-y += ../common/cbmem.c emi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memory.c</span><br><span> romstage-y += ../common/gpio.c gpio.c</span><br><span> romstage-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c</span><br><span>diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c</span><br><span>index e37fd56..6c36feb 100644</span><br><span>--- a/src/soc/mediatek/mt8183/emi.c</span><br><span>+++ b/src/soc/mediatek/mt8183/emi.c</span><br><span>@@ -13,9 +13,278 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span> #include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/infracfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_pi_api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_register.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct emi_regs *emi_regs = (void *)EMI_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+const u8 phy_mapping[CHANNEL_MAX][16] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [CHANNEL_A] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, 0, 2, 4, 3, 7, 5, 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ 9, 8, 12, 11, 10, 15, 13, 14</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ [CHANNEL_B] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 1, 5, 6, 3, 7, 4, 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ 9, 8, 12, 15, 11, 14, 13, 10</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_set_broadcast(u32 bOnOff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->dramc_wbr, bOnOff);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 dramc_get_broadcast(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return read32(&mt8183_infracfg->dramc_wbr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u64 get_ch_rank_size(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 shift_for_16bit = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 col_bit, row_bit;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_cona = read32(&emi_regs->cona);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ shift_for_16bit = (emi_cona & 0x2) ? 0 : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ col_bit = ((emi_cona >> (chn * 16 + rank * 2 + 4)) & 0x03) + 9;</span><br><span style="color: hsl(120, 100%, 40%);">+ row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) +</span><br><span style="color: hsl(120, 100%, 40%);">+ ((emi_cona >> (12 + chn*16 + rank * 2)) & 0x03)) + 13;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* data width (bytes) * 8 banks */</span><br><span style="color: hsl(120, 100%, 40%);">+ return ((u64)(1 << (row_bit + col_bit))) *</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u64)(4 >> shift_for_16bit) * 8);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_get_rank_size(u64 *dram_rank_size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ch0_rank0_size, ch0_rank1_size, ch1_rank0_size, ch1_rank1_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ch_rank0_size = 0, ch_rank1_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_cona = read32(&emi_regs->cona);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_conh = read32(&emi_regs->conh);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[0] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[1] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ch0_rank0_size = (emi_conh >> 16) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ ch0_rank1_size = (emi_conh >> 20) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ ch1_rank0_size = (emi_conh >> 24) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ ch1_rank1_size = (emi_conh >> 28) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CH0 EMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch0_rank0_size == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = get_ch_rank_size(CHANNEL_A, RANK_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = (ch0_rank0_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* dual rank enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((emi_cona & (1 << 17)) != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch0_rank1_size == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = (ch0_rank1_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[0] = ch_rank0_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[1] = ch_rank1_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch1_rank0_size == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = get_ch_rank_size(CHANNEL_B, RANK_0);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = (ch1_rank0_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((emi_cona & (1 << 16)) != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch1_rank1_size == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = get_ch_rank_size(CHANNEL_B, RANK_1);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = (ch1_rank1_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[0] += ch_rank0_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[1] += ch_rank1_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> size_t sdram_size(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return (size_t)4 * GiB;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t dram_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rank_size[RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_get_rank_size(&rank_size[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < RANK_MAX; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_size += rank_size[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("rank%d size:0x%llx\n", i, rank_size[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return dram_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_rank_info_to_conf(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u4value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CONA 17th bit 0: Disable dual rank mode</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1: Enable dual rank mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ u4value = ((params->emi_cona_val & (0x1 << 17)) >> 17) ? 0 : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_MRR_pinmux_mapping(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 *map = phy_mapping[chn];</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[0] << 0) | (map[1] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[2] << 16) | (map[3] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[4] << 0) | (map[5] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[6] << 16) | (map[7] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[8] << 0) | (map[9] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[10] << 16) | (map[11] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[12] << 0) | (map[13] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[14] << 16) | (map[15] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void global_option_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rank_info_to_conf(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_MRR_pinmux_mapping();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_esl_setting1(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cona, 0xa053a154);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conb, 0x17283544);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conc, 0x0a1a0b1a);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cond, 0x3657587a);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cone, 0x80400148);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conf, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cong, 0x2b2b2a38);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conh, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->coni, 0x00008803);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conm, 0x000001ff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conn, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->mdct, 0x11338c17);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->mdct_2nd, 0x00001112);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocl, 0xa8a8a8a8);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocl_2nd, 0x25252525);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocm, 0xa8a8a8a8);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocm_2nd, 0x25252525);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->testb, 0x00060037);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->testc, 0x38460000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->testd, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arba, 0x4020524f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbb, 0x4020504f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbc, 0xa0a050c6);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbd, 0x000070cc);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbe, 0x40406045);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbf, 0xa0a070d5);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbg, 0xa0a0504f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbh, 0xa0a0504f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbi, 0x00007108);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbi_2nd, 0x00007108);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->slct, 0x0001ff00);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_cona, 0x0400a051);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_conb, 0x00ff2048);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_conc, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_mdct, 0x88008817);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_testb, 0x00030027);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_testc, 0x38460002);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_testd, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_md_pre_mask, 0x00000f00);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_md_pre_mask_shf, 0x00000b00);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbi, 0x20406188);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbi_2nd, 0x20406188);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbj, 0x3719595e);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbj_2nd, 0x3719595e);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbk, 0x64f3fc79);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbk_2nd, 0x64f3fc79);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_slct, 0x00080888);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arb_ref, 0x82410222);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_emi_shf0, 0x8a228c17);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_rkarb0, 0x0006002f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_rkarb1, 0x01010101);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_rkarb2, 0x10100820);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_eco3, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_esl_setting2(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_conc, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conm, 0x05ff);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_esl_setting1();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cona, params->emi_cona_val);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conf, params->emi_conf_val);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conh, params->emi_conh_val);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].emi.chn_cona, params->chn_emi_cona_val[chn]);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].emi.chn_conc, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_init2(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_esl_setting2();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0, 0x0A000705);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_3rd, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EMI QoS 0.5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_2nd, 0x00030023);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_4th, 0x00c00023);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_5th, 0x00240023);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_init_pre_settings(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1F << 8) | (0x1f << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 19) | (0xa << 8) | (0xa << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void init_dram(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ global_option_init(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_init(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_init_pre_settings();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_init2(params);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_set_emi(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ init_dram(params);</span><br><span> }</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h</span><br><span>new file mode 100644</span><br><span>index 0000000..e699e80</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _DRAMC_COMMON_MT8183_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _DRAMC_COMMON_MT8183_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRAM_DFS_SHUFFLE_MAX 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_A = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_B,</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_0 = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum dram_odt_type {</span><br><span style="color: hsl(120, 100%, 40%);">+ ODT_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ODT_ON</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQ_DATA_WIDTH = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_BIT_NUMBER = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER)</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Internal CBT mode enum</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to</span><br><span style="color: hsl(120, 100%, 40%);">+ * differentiate between mixed vs non-mixed LP4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to</span><br><span style="color: hsl(120, 100%, 40%);">+ * store each rank's CBT mode type</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_NORMAL_MODE = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_BYTE_MODE1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _DRAMC_COMMON_MT8183_H_ */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>new file mode 100644</span><br><span>index 0000000..e24bd6c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>@@ -0,0 +1,135 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _DRAMC_PI_API_MT8183_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _DRAMC_PI_API_MT8183_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define dramc_show(_x_...) printk(BIOS_INFO, _x_)</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_DEBUG_DRAM)</span><br><span style="color: hsl(120, 100%, 40%);">+#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define dramc_dbg(_x_...)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISABLE 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DATLAT_TAP_NUMBER 32</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_CMP_CPT_WAIT_LOOP 10000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TIME_OUT_CNT 100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRAMC_BROADCAST_ON 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRAMC_BROADCAST_OFF 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_BACKUP_REG_CNT 32</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum dram_te_op {</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_WRITE_READ_CHECK = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_READ_CHECK</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DBI_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ DBI_ON</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_0 = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ_DQS_MOVE_DQ_ONLY = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ_DQS_MOVE_DQM_ONLY,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ_DQS_MOVE_DQ_DQM</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_CA_FINE_TUNE_DELAY = 63,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_CS_FINE_TUNE_DELAY = 63,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_CLK_FINE_TUNE_DELAY = 31,</span><br><span style="color: hsl(120, 100%, 40%);">+ CATRAINING_NUM = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ PASS_RANGE_NA = 0x7fff</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_ON = 1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_FIXOFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_FIXON,</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_DYNAMIC</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_PATTERN_NUM = 0x23,</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_GOLDEND_DQSCNT = 0x4646</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPCAL_STAGE_DRVP = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPCAL_STAGE_DRVN,</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPCAL_STAGE_TRACKING</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_COARSE_STEP = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FINE_START = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FINE_END = 32,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FINE_STEP = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FREQ_DIV = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DQS_CTL_LOOP = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DLY_DQSIENSTB_LOOP = 32</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SAVE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ RESTORE_VALUE</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQ_DIV_SHIFT = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ OEN_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_DELAY_2T = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_DELAY_0P5T = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_DELAY = ((DQS_DELAY_2T << DQ_DIV_SHIFT) + DQS_DELAY_0P5T) << 5,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_OEN_DELAY_2T = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_OEN_DELAY_0P5T = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ SELPH_DQS0 = (DQS_DELAY_2T << 0) | (DQS_DELAY_2T << 4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (DQS_DELAY_2T << 8) | (DQS_DELAY_2T << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (DQS_OEN_DELAY_2T << 16) | (DQS_OEN_DELAY_2T << 20) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (DQS_OEN_DELAY_2T << 24) | (DQS_OEN_DELAY_2T << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ SELPH_DQS1 = (DQS_DELAY_0P5T << 0) | (DQS_DELAY_0P5T << 4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (DQS_DELAY_0P5T << 8) | (DQS_DELAY_0P5T << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (DQS_OEN_DELAY_0P5T << 16) | (DQS_OEN_DELAY_0P5T << 20) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (DQS_OEN_DELAY_0P5T << 24) | (DQS_OEN_DELAY_0P5T << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_get_rank_size(u64 *dram_rank_size);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_set_broadcast(u32 onoff);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 dramc_get_broadcast(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _DRAMC_PI_API_MT8183_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>index edc27a8..c3c8e81 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>@@ -18,7 +18,27 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_common_mt8183.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct sdram_params {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 impedance[2][4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cbt_cs[CHANNEL_MAX][RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cbt_mr12[CHANNEL_MAX][RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 clk_delay;</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 dqs_delay[CHANNEL_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_cona_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_conh_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_conf_val;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 chn_emi_cona_val[CHANNEL_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cbt_mode_extern;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 delay_cell_unit;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int complex_mem_test(u8 *start, unsigned int len);</span><br><span> size_t sdram_size(void);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct sdram_params *get_sdram_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_set_emi(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_mem_init(const struct sdram_params *params);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_EMI_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c</span><br><span>new file mode 100644</span><br><span>index 0000000..643ca6b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/memory.c</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_mem_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* memory calibration */</span><br><span style="color: hsl(120, 100%, 40%);">+ mt_set_emi(params);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28835">change 28835</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28835"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea </div>
<div style="display:none"> Gerrit-Change-Number: 28835 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>