<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28854">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_THERM_INTERRUPT to x86/msr.h<br><br>Change-Id: I9d0a36d07d114f48894977c0b80ff0ff9f776ed4<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/cannonlake/include/soc/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/skylake/include/soc/msr.h<br>10 files changed, 1 insertion(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28854/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index 87f0525..29a868d 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 135a3f8..169744a 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index d1924cf..7533a6b 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -42,7 +42,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index f26ac0f..de1282b 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 606a65c..4a40ac3 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 31449ed..b37eb83 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -24,6 +24,7 @@</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define IA32_PERF_STATUS 0x198</span><br><span> #define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define MSR_IA32_PAT 0x277</span><br><span> #define IA32_BIOS_UPDT_TRIG 0x79</span><br><span> #define IA32_BIOS_SIGN_ID 0x8b</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index f26ec66..5e32e15 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -34,7 +34,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>index 6617d7f..86e13ab 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 8a07865..cc87871 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -36,7 +36,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index 780f94f..bfe3671 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span> #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28854">change 28854</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9d0a36d07d114f48894977c0b80ff0ff9f776ed4 </div>
<div style="display:none"> Gerrit-Change-Number: 28854 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>