<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28856">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_ENERGY_PERF_BIAS to x86/msr.h<br><br>Change-Id: Ia0b116d4865c1e964e3ebf296cb379a664096c79<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/haswell/haswell_init.c<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_2065x/model_2065x_init.c<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/cpu/intel/model_206ax/model_206ax_init.c<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/cannonlake/cpu.c<br>M src/soc/intel/cannonlake/include/soc/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/skylake/cpu.c<br>M src/soc/intel/skylake/include/soc/msr.h<br>16 files changed, 16 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28856/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index eb4d6a9..46c7a65 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -26,10 +26,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 194fc12..5d9b8d3 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -27,10 +27,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index b4e8c88..97c1abe 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -41,10 +41,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span>diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c</span><br><span>index 5ea8535..3d353ba 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell_init.c</span><br><span>+++ b/src/cpu/intel/haswell/haswell_init.c</span><br><span>@@ -649,10 +649,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "haswell: energy policy set to %u\n",</span><br><span> policy);</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index 445d313..aeb113a 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -28,10 +28,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c</span><br><span>index 322e814..222c2ed 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x_init.c</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x_init.c</span><br><span>@@ -231,10 +231,10 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",</span><br><span> policy);</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index cbfa6ae..2f28799 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -26,10 +26,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>index 3cc8d82..194114d 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>@@ -401,10 +401,10 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",</span><br><span> policy);</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 02c698d..9148349 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -34,6 +34,10 @@</span><br><span> #define MSR_IA32_MPERF 0xe7</span><br><span> #define MSR_IA32_APERF 0xe8</span><br><span> #define IA32_MCG_CAP 0x179</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_ENERGY_PERF_BIAS 0x1b0</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define MSR_IA32_PM_ENABLE 0x770</span><br><span> #define MSR_IA32_HWP_CAPABILITIES 0x771</span><br><span> #define MSR_IA32_HWP_REQUEST 0x774</span><br><span>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c</span><br><span>index ee1fd52..4c1b3fd 100644</span><br><span>--- a/src/soc/intel/broadwell/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/cpu.c</span><br><span>@@ -546,10 +546,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 437aef0..40a9340 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -33,10 +33,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRRphysBase_MSR 0x1f4</span><br><span> #define EMRRphysMask_MSR 0x1f5</span><br><span>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c</span><br><span>index ba87045..96b82fd 100644</span><br><span>--- a/src/soc/intel/cannonlake/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/cpu.c</span><br><span>@@ -126,10 +126,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> }</span><br><span> </span><br><span> static void configure_c_states(void)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>index 86e13ab..f8a342c 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>@@ -20,10 +20,6 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f9</span><br><span> #define MSR_VR_MISC_CONFIG2 0x636</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index d63cc04..58d4cfe 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -35,10 +35,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRR_PHYS_BASE_MSR 0x1f4</span><br><span> #define EMRR_PHYS_MASK_MSR 0x1f5</span><br><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 417c4bc..605dc00 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -353,10 +353,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index bfe3671..a371e47 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -24,10 +24,6 @@</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28856">change 28856</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28856"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia0b116d4865c1e964e3ebf296cb379a664096c79 </div>
<div style="display:none"> Gerrit-Change-Number: 28856 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>