<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28841">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add DDR driver of rx dqs gating calibration part<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br> patches.<br><br>Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f<br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/dramc_pi_basic_api.c<br>M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c<br>M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h<br>3 files changed, 666 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/28841/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c</span><br><span>index 4c95814..74eddd5 100644</span><br><span>--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c</span><br><span>@@ -19,6 +19,16 @@</span><br><span> #include <soc/dramc_register.h></span><br><span> #include <soc/dramc_pi_api.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_save_restore_multi_reg(u8 type, u32 *store_mem,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 **addr, u32 count)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < count; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (type == SAVE_VALUE)</span><br><span style="color: hsl(120, 100%, 40%);">+ store_mem[i] = read32(addr[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(addr[i], store_mem[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage)</span><br><span> {</span><br><span> u8 vref_sel = 0;</span><br><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>index 7b42287..159d72a 100644</span><br><span>--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>@@ -310,6 +310,657 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void rx_dqs_isi_pulse_cg_switch(u8 chn, u8 flag)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("CH%d RX DQS ISI pulse CG: %s\n", chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ (flag == ENABLE) ? "enable" : "disable");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 1 << 5, flag << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 1 << 5, flag << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_set_rank_engine2(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dramctrl, 0x1 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ rank << TEST2_4_TESTAGENTRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_engine2_init(u8 chn, u8 rank, u32 size, u8 testaudpat)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 pat0 = 0x55;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 pat1 = 0xaa;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 addr = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 log2loopcount = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_rank_engine2(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.dummy_rd,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DQSG_DMYRD_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DQSG_DMYWR_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DUMMY_RD_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].nao.testchip_dma1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TESTAUDPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ log2loopcount << TEST2_3_TESTCNT_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((testaudpat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (pat0 << TEST2_0_PAT0_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (pat1 << TEST2_0_PAT1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.test2_1, (addr << 4) & 0x00ffffff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.test2_2, (size << 4) & 0x00ffffff);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDMODE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDBITINV_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTXTALKPAT_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ (((testaudpat == 0) ? 1 : 0) << TEST2_4_TESTXTALKPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (testaudpat << TEST2_4_TESTAUDMODE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (testaudpat << TEST2_4_TESTAUDBITINV_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (testaudpat == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTSSOPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.perfctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << PERFCTL0_RWOFOEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (testaudpat == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x11 << TEST2_4_TESTAUDINIT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xd << TEST2_4_TESTAUDINC_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_engine2_check_complete(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4loop_count = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ while ((read32(&ch[chn].nao.testrpt) & (0x1 << 0)) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ u4loop_count++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("MEASURE_A timeout\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4result = 0xffffffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (wr == TE_OP_READ_CHECK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTAUDMODE_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (wr == TE_OP_WRITE_READ_CHECK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TEST2W_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_check_complete(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TEST1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* do Read test */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TEST2R_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_check_complete(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ u4result = read32(&ch[chn].nao.cmp_err);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return u4result;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_engine2_end(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *pass_count, u8 *dly_fine_xt, u32 *coarse_tune, u8 *dqs_high)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 debug_cnt_perbyte;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pass_count_1[DQS_NUMBER], min_coarse_tune2t_1[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune0p5t_1[DQS_NUMBER], min_fine_tune_1[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt_perbyte = (u16) debug_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((dqs_result_r == 0) && (dqs_result_f == 0) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (debug_cnt_perbyte == GATING_GOLDEND_DQSCNT)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pass_begin[dqs] == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_begin[dqs] = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count_1[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune2t_1[dqs] = dly_coarse_large;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune0p5t_1[dqs] = dly_coarse_0p5t;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_fine_tune_1[dqs] = *dly_fine_xt;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, dly_coarse_large,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t, *dly_fine_xt);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pass_begin[dqs] == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count_1[dqs]++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pass_begin[dqs] == 1) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (pass_count_1[dqs] * DQS_GW_FINE_STEP > 32))</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pass_count_1[0] * DQS_GW_FINE_STEP > 32) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (pass_count_1[1] * DQS_GW_FINE_STEP > 32)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("All bytes gating window > 1 "</span><br><span style="color: hsl(120, 100%, 40%);">+ "coarse_tune, Early break\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ *dly_fine_xt = 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ *coarse_tune = 42;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_fine_xt, u8 *dqs_high, u8 *dly_coarse_large_cnt,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt, u8 *dqs_trans)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dqs_cnt = read32(&ch[chn].phy_nao.misc_phy_stben_b[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt = (dqs_cnt >> 16) & 3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqs_cnt == 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs]++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqs_high[dqs] * DQS_GW_FINE_STEP <= 16)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dqs_cnt) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_cnt[dqs] = dly_coarse_large;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt[dqs] = dly_coarse_0p5t;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[dqs] = dly_fine_xt;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_trans[dqs] = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_trans[dqs]++;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dram_phy_reset(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_set_gating_mode(u8 chn, u8 mode)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref = 0, burst = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mode) {</span><br><span style="color: hsl(120, 100%, 40%);">+ vref = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ burst = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pass_begin[DQS_NUMBER], pass_count[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ min_fine_tune[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_fine_tune_p1[DQS_NUMBER], best_coarse_tune0p5t_p1[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_coarse_large_rodt[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_coarse_large_rodt_p1[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt_p1[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_start = 18, coarse_end = coarse_start + 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 debug_cnt[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs_high[DQS_NUMBER], dqs_transition[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_large_cnt[DQS_NUMBER], dly_coarse_0p5t_cnt[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mr1_value[FSP_MAX] = { 0x56, 0x56 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value_store[MAX_BACKUP_REG_CNT];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *regs_backup[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.stbcal1,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.ddrconf0,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.spcmd,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.refctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_save_restore_multi_reg(SAVE_VALUE, value_store,</span><br><span style="color: hsl(120, 100%, 40%);">+ regs_backup, ARRAY_SIZE(regs_backup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_dqs_isi_pulse_cg_switch(chn, DISABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value[1] | 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_gating_onoff(chn, GATING_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBENCMPEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBCNT_LATCH_EN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_DM4TO1MODE_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(4);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ rank << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_init(chn, rank, 0x23, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_begin[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_transition[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_cnt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("[Gating]\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end;</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune += DQS_GW_COARSE_STEP) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_large_rodt = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_0p5t_rodt = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_large_rodt_p1 = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_0p5t_rodt_p1 = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_large_p1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune + DQS_GW_FREQ_DIV) / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_0p5t_p1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune + DQS_GW_FREQ_DIV) % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (value >= 11) {</span><br><span style="color: hsl(120, 100%, 40%);">+ value -= 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_rodt = value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_rodt =</span><br><span style="color: hsl(120, 100%, 40%);">+ value - (dly_coarse_large_rodt << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_rodt_p1 = value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_rodt_p1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ value - (dly_coarse_large_rodt_p1 << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_large <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_large <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_0p5t <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_0p5t <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 dly_fine_xt = DQS_GW_FINE_START;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt < DQS_GW_FINE_END;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt += DQS_GW_FINE_STEP) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_gating_mode(chn, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt | (dly_fine_xt << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_run(chn, TE_OP_READ_CHECK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) &</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STBERR_RK_R_STBERR_RK_R_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) &</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STBERR_RK_F_STBERR_RK_F_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt[0] &= 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_gating_mode(chn, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_run(chn, TE_OP_READ_CHECK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ find_dly_tune(chn, dly_coarse_large, dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt, dqs_high, dly_coarse_large_cnt,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt, dqs_transition);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("%d %d %d |",</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large, dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("%X ", debug_cnt[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show(" |");</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("(%X %X)",</span><br><span style="color: hsl(120, 100%, 40%);">+ (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff,</span><br><span style="color: hsl(120, 100%, 40%);">+ (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ find_gating_window(result_r, result_f, &debug_cnt[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large, dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ &pass_begin[0], &pass_count[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ &dly_fine_xt, &coarse_tune, &dqs_high[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.dummy_rd, dummy_rd_backup);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count[dqs] = dqs_transition[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ min_fine_tune[dqs] = dly_fine_tune_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tmp_value = min_fine_tune[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune_p1[dqs] = best_fine_tune[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_offset = tmp_value / RX_DLY_DQSIENSTB_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value = min_coarse_tune0p5t[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t[dqs] = tmp_value % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_offset = tmp_value / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune2t[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value = best_coarse_tune0p5t[dqs] + DQS_GW_FREQ_DIV;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t_p1[dqs] = tmp_value % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_offset = tmp_value / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("best DQS%d dly(2T, 0.5T, fine tune)"</span><br><span style="color: hsl(120, 100%, 40%);">+ " = (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, best_coarse_tune2t[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("best DQS%d best coarse dly"</span><br><span style="color: hsl(120, 100%, 40%);">+ "(2T, 0.5T, fine tune) = (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, best_coarse_tune2t_p1[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t_p1[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_save_restore_multi_reg(RESTORE_VALUE, value_store,</span><br><span style="color: hsl(120, 100%, 40%);">+ regs_backup, ARRAY_SIZE(regs_backup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value[1] & 0x7f);</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_dqs_isi_pulse_cg_switch(chn, ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tmp_value = (best_coarse_tune2t[dqs] << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ + best_coarse_tune0p5t[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tmp_value >= 11) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value -= 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt[dqs] = tmp_value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value - (best_coarse_large_rodt[dqs] << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value = (best_coarse_tune2t_p1[dqs] << 3) +</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t_p1[dqs] - 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt_p1[dqs] = tmp_value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt_p1[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value - (best_coarse_large_rodt_p1[dqs] << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("best RODT dly(2T, 0.5T) = (%d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt_p1[dqs] = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt_p1[dqs] = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("RxdqsGatingCal Error: best_coarse_tune2t:%d"</span><br><span style="color: hsl(120, 100%, 40%);">+ " is already 0. RODT cannot be -1 coarse tune\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune[0] | (best_fine_tune[1] << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_dqs_gating_post_process(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs, rank_rx_dvs, dqsinctl, rank;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 read_dqsinctl, rankinctl_root, xrtr2r, reg_tx_dly_dqsgated_min = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 txdly_cal_min = 0xff, txdly_cal_max = 0, tx_dly_dqs_gated = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 best_coarse_tune2t[RANK_MAX][DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 best_coarse_tune2t_p1[RANK_MAX][DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_rx_dvs = reg_tx_dly_dqsgated_min - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_BX_DQ7_R_DMRANKRXDVS_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_rx_dvs << SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dqsg0 = read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[rank][dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (dqsg0 >> (dqs * 8)) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[rank][dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ ((dqsg0 >> (dqs * 8)) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("rank%d best DQS%d dly(2T, (P1)2T) = (%d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ rank, dqs, best_coarse_tune2t[rank][dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[rank][dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_dly_dqs_gated = best_coarse_tune2t[rank][dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_min = MIN(txdly_cal_min, tx_dly_dqs_gated);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_dly_dqs_gated = best_coarse_tune2t_p1[rank][dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_max = MAX(txdly_cal_max, tx_dly_dqs_gated);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dqsinctl = reg_tx_dly_dqsgated_min - txdly_cal_min;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("dqsinctl:%d, tx_dly_dqsgated_min %d, txdly_cal_min %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqsinctl != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_min += dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_max += dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("Rank: %d\n", rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[rank][dqs] += dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[rank][dqs] += dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("best DQS%d dly(2T) = (%d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, best_coarse_tune2t[rank][dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("best DQS%d P1 dly(2T) = (%d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, best_coarse_tune2t_p1[rank][dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t[rank][0] << 0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t[rank][1] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t_p1[rank][0] << 4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t_p1[rank][1] << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl = (read32(&ch[chn].ao.shu[0].rk[0].dqsctl) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK) - dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read_dqsinctl >= 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ rankinctl_root = read_dqsinctl - 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ rankinctl_root = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DQSINCTL < 3, Risk for supporting 1066/RL8\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_PHY_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_MASK | SHU_RANKCTL_RANKINCTL_ROOT1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (read_dqsinctl << SHU_RANKCTL_RANKINCTL_PHY_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (rankinctl_root << SHU_RANKCTL_RANKINCTL_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (rankinctl_root << SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ xrtr2r = MIN(8 + txdly_cal_max + 1, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ACTIM_XRT_XRTR2R_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ xrtr2r << SHU_ACTIM_XRT_XRTR2R_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("TX_dly_DQS gated check: min %d max %d, ChangeDQSINCTL=%d\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ "DQSINCTL=%d, RANKINCTL=%d, XRTR2R=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_min, txdly_cal_max, dqsinctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl, rankinctl_root, xrtr2r);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void dramc_calibrate_all_channels(const struct sdram_params *pams)</span><br><span> {</span><br><span> for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {</span><br><span>@@ -319,6 +970,9 @@</span><br><span> cmd_bus_training(chn, rk, pams);</span><br><span> dramc_write_leveling(chn, rk, pams->wr_level);</span><br><span> auto_refresh_switch(chn, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_dqs_gating_cal(chn, rk);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_dqs_gating_post_process(chn);</span><br><span> }</span><br><span> }</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>index f5b6251..761fff6 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>@@ -140,4 +140,6 @@</span><br><span> void dramc_sw_impedance(const struct sdram_params *params);</span><br><span> void dramc_apply_pre_calibration_config(void);</span><br><span> void dramc_calibrate_all_channels(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_save_restore_multi_reg(u8 type, u32 *store_mem,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 **addr, u32 count);</span><br><span> #endif /* _DRAMC_PI_API_MT8183_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28841">change 28841</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28841"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f </div>
<div style="display:none"> Gerrit-Change-Number: 28841 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>