<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28852">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_{FEATURE_CONTROL,MCG_CAP} to x86/msr.h<br><br>Change-Id: I36a84896187558e16f6a960839c890a89ff2ac09<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/common/common_init.c<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/haswell/haswell_init.c<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/baytrail/romstage/cache_as_ram.inc<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/common/block/sgx/sgx.c<br>M src/soc/intel/common/block/vmx/vmx.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>16 files changed, 15 insertions(+), 43 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28852/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c</span><br><span>index 8dd8559..98b7f58 100644</span><br><span>--- a/src/cpu/intel/common/common_init.c</span><br><span>+++ b/src/cpu/intel/common/common_init.c</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include "common.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span> #define CPUID_VMX (1 << 5)</span><br><span> #define CPUID_SMX (1 << 6)</span><br><span> </span><br><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index e65b370..7db870d 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -20,9 +20,6 @@</span><br><span> /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */</span><br><span> #define SANDYBRIDGE_BCLK 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 87daeac..953fdca 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -21,9 +21,6 @@</span><br><span> /* Rangeley bus clock is fixed at 100MHz */</span><br><span> #define RANGELEY_BCLK 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 8498c1a..51a0deb 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -35,9 +35,6 @@</span><br><span> #define HASWELL_BCLK 100</span><br><span> </span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span>diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c</span><br><span>index 24de43e..5ea8535 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell_init.c</span><br><span>+++ b/src/cpu/intel/haswell/haswell_init.c</span><br><span>@@ -661,11 +661,10 @@</span><br><span> static void configure_mca(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned int mcg_cap_msr = 0x179;</span><br><span> int i;</span><br><span> int num_banks;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(mcg_cap_msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MCG_CAP);</span><br><span> num_banks = msr.lo & 0xff;</span><br><span> msr.lo = msr.hi = 0;</span><br><span> /* TODO(adurbin): This should only be done on a cold boot. Also, some</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index f87ba77..521e806 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -20,9 +20,6 @@</span><br><span> /* Nehalem bus clock is fixed at 133MHz */</span><br><span> #define NEHALEM_BCLK 133</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 98203b6..9ab7466 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -20,9 +20,6 @@</span><br><span> /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */</span><br><span> #define SANDYBRIDGE_BCLK 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span>@@ -39,7 +36,6 @@</span><br><span> #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index a5a9de3..7391ac5 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -37,10 +37,6 @@</span><br><span> #define G_SMRAME (1 << 3)</span><br><span> #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_CONTROL_LOCK_BIT (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMRR_ENABLE (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> struct ied_header {</span><br><span> char signature[10];</span><br><span> u32 size;</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index dcd23ee..f9d8f50 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -14,11 +14,20 @@</span><br><span> </span><br><span> /* Page attribute type MSR */</span><br><span> #define IA32_PLATFORM_ID 0x17</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define FEATURE_CONTROL_LOCK_BIT (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FEATURE_ENABLE_VMX (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMRR_ENABLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_SMX (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_IA32_PAT 0x277</span><br><span> #define IA32_BIOS_UPDT_TRIG 0x79</span><br><span> #define IA32_BIOS_SIGN_ID 0x8b</span><br><span> #define MSR_IA32_MPERF 0xe7</span><br><span> #define MSR_IA32_APERF 0xe8</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP 0x179</span><br><span> #define MSR_IA32_PM_ENABLE 0x770</span><br><span> #define MSR_IA32_HWP_CAPABILITIES 0x771</span><br><span> #define MSR_IA32_HWP_REQUEST 0x774</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>index dcb6296..fea8686 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>@@ -14,6 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span>@@ -35,7 +36,6 @@</span><br><span> </span><br><span> #define NoEvictMod_MSR 0x2e0</span><br><span> #define BBL_CR_CTL3_MSR 0x11e</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCG_CAP_MSR 0x179</span><br><span> </span><br><span> /* Save the BIST result. */</span><br><span> movl %eax, %ebp</span><br><span>@@ -64,7 +64,7 @@</span><br><span> </span><br><span> post_code(0x22)</span><br><span> /* Zero the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MCG_CAP_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_MCG_CAP, %ecx</span><br><span> rdmsr</span><br><span> movzx %al, %ebx</span><br><span> /* First variable MTRR. */</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 41ce17c..13cc6f2 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -18,9 +18,6 @@</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index e1fc431..15aac62 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -17,13 +17,6 @@</span><br><span> #define SOC_INTEL_COMMON_MSR_H</span><br><span> </span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_CONTROL_LOCK (1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_ENABLE_VMX (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */</span><br><span>@@ -46,7 +39,6 @@</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL</span><br><span> #define FEATURE_CONFIG_LOCK (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span> #define SMM_MCA_CAP_MSR 0x17d</span><br><span> #define SMM_CPU_SVRSTR_BIT 57</span><br><span> #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))</span><br><span>diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>index daedcfc..6050dec 100644</span><br><span>--- a/src/soc/intel/common/block/sgx/sgx.c</span><br><span>+++ b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>@@ -137,7 +137,7 @@</span><br><span> </span><br><span> msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span> /* Only enable it when it is not locked */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) {</span><br><span> msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */</span><br><span> wrmsr(IA32_FEATURE_CONTROL, msr);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c</span><br><span>index 591ffbc..2cffdab 100644</span><br><span>--- a/src/soc/intel/common/block/vmx/vmx.c</span><br><span>+++ b/src/soc/intel/common/block/vmx/vmx.c</span><br><span>@@ -58,7 +58,7 @@</span><br><span> msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span> </span><br><span> /* Only enable it when it is not locked */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) {</span><br><span> /* Enable VMX */</span><br><span> msr.lo |= FEATURE_ENABLE_VMX;</span><br><span> wrmsr(IA32_FEATURE_CONTROL, msr);</span><br><span>@@ -68,5 +68,5 @@</span><br><span> msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span> printk(BIOS_DEBUG, "VMX status: %s, %s\n",</span><br><span> (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled",</span><br><span style="color: hsl(0, 100%, 40%);">- (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked");</span><br><span style="color: hsl(120, 100%, 40%);">+ (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked");</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index a49e225..c816ea4 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -20,9 +20,6 @@</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index af1db04..d81ed85 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> </span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span> #define IA32_PERF_CTL 0x199</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define IA32_MC0_CTL 0x400</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28852">change 28852</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I36a84896187558e16f6a960839c890a89ff2ac09 </div>
<div style="display:none"> Gerrit-Change-Number: 28852 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>