<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28860">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_PLATFORM_DCA_CAP to x86/msr.h<br><br>Change-Id: I2f97c34449b70f8c56da3a833cd0af497df1909d<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/cannonlake/include/soc/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/skylake/include/soc/msr.h<br>10 files changed, 1 insertion(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/28860/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index f45081e..020b72d 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> </span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index b5547d0..5dfe016 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -25,7 +25,6 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> </span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index fef3e1b..4ccb1c1 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -39,7 +39,6 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index 9b7c876..11d86cd 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 5c90133..09aa484 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> </span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 3bc8584..d15d4cb 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -39,6 +39,7 @@</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span> #define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define IA32_MC0_CTL 0x400</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> #define IA32_PM_ENABLE 0x770</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index d6f21ea..c93d292 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define EMRRphysBase_MSR 0x1f4</span><br><span> #define EMRRphysMask_MSR 0x1f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_EMRRphysBase_MSR 0x2f4</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>index 0c7852a..e3bd5f6 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_VR_MISC_CONFIG2 0x636</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 962049f..082117c 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -37,7 +37,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define EMRR_PHYS_BASE_MSR 0x1f4</span><br><span> #define EMRR_PHYS_MASK_MSR 0x1f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index a1bb0fc..6da9325 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28860">change 28860</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2f97c34449b70f8c56da3a833cd0af497df1909d </div>
<div style="display:none"> Gerrit-Change-Number: 28860 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>