<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28839">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add DDR driver of cmd bus training part<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br> patches.<br><br>Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d<br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c<br>M src/soc/mediatek/mt8183/emi.c<br>M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h<br>3 files changed, 94 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28839/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>index c5ec9c7..0542baa 100644</span><br><span>--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>@@ -20,6 +20,88 @@</span><br><span> #include <soc/dramc_register.h></span><br><span> #include <soc/dramc_pi_api.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void auto_refresh_switch(u8 chn, u8 option)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ (option ? 0 : 1) << REFCTRL0_REFDIS_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (option == DISABLE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* because HW will actually disable autorefresh</span><br><span style="color: hsl(120, 100%, 40%);">+ * after refresh_queue empty, we need to wait quene empty */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(((read32(&ch[chn].nao.misc_statusa) &</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STATUSA_REFRESH_QUEUE_CNT_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT)*4);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_cke_fix_onoff(int option, u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 on = 0, off = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* if CKE is dynamic, set both CKE fix On and Off as 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (option != CKE_DYNAMIC) {</span><br><span style="color: hsl(120, 100%, 40%);">+ on = option;</span><br><span style="color: hsl(120, 100%, 40%);">+ off = (1 - option);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.ckectrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rank = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_cke_fix_onoff(CKE_FIXON, chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSMA_MASK, mr_idx << MRS_MRSMA_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSOP_MASK, value << MRS_MRSOP_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while ((read32(&ch[chn].nao.spcmdresp) & 1) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("wait MRW command fired\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rank = (read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK) >> MRS_MRSRK_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("Write Rank%d MR%d =0x%x\n", rank, mr_idx, value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mr_idx, u8 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn, mr_idx, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void cmd_bus_training(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cbt_cs, mr12_value;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbt_cs = params->cbt_cs[chn][rank];</span><br><span style="color: hsl(120, 100%, 40%);">+ mr12_value = params->cbt_mr12[chn][rank];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("start chn:%d, rank:%d, cbt_cs:0x%x, mr12_value:0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, cbt_cs, mr12_value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* cbt_adjust_cs */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* cbt_set_vref */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void dramc_read_dbi_onoff(u8 onoff)</span><br><span> {</span><br><span> for (u8 chn = 0; chn < CHANNEL_MAX; chn++)</span><br><span>@@ -203,3 +285,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_calibrate_all_channels(const struct sdram_params *pams)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("start K ch:%d, rank:%d\n", chn, rk);</span><br><span style="color: hsl(120, 100%, 40%);">+ auto_refresh_switch(chn, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd_bus_training(chn, rk, pams);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c</span><br><span>index ba913a2..eb75890 100644</span><br><span>--- a/src/soc/mediatek/mt8183/emi.c</span><br><span>+++ b/src/soc/mediatek/mt8183/emi.c</span><br><span>@@ -296,6 +296,7 @@</span><br><span> static void do_calib(const struct sdram_params *params)</span><br><span> {</span><br><span> dramc_apply_pre_calibration_config();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_calibrate_all_channels(params);</span><br><span> }</span><br><span> </span><br><span> void mt_set_emi(const struct sdram_params *params)</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>index ed9eb81..f5b6251 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>@@ -139,4 +139,5 @@</span><br><span> u32 dramc_get_broadcast(void);</span><br><span> void dramc_sw_impedance(const struct sdram_params *params);</span><br><span> void dramc_apply_pre_calibration_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_calibrate_all_channels(const struct sdram_params *params);</span><br><span> #endif /* _DRAMC_PI_API_MT8183_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28839">change 28839</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28839"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d </div>
<div style="display:none"> Gerrit-Change-Number: 28839 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>