<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28843">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add DDR driver of rx datlat calibration part<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br> patches.<br><br>Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97<br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c<br>1 file changed, 78 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/28843/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>index f6ab9a0..2295f39 100644</span><br><span>--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>@@ -1701,6 +1701,81 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dle_factor_handler(u8 chn, u8 curr_val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ curr_val = MAX(curr_val, 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].conf[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (SHU_CONF1_DATLAT_MASK) | (SHU_CONF1_DATLAT_DSEL_MASK) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (SHU_CONF1_DATLAT_DSEL_PHY_MASK),</span><br><span style="color: hsl(120, 100%, 40%);">+ (curr_val << SHU_CONF1_DATLAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((curr_val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((curr_val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 dramc_rx_datlat_cal(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 err = 0xffffffff, datlat_begin = 7;</span><br><span style="color: hsl(120, 100%, 40%);">+ s32 datlat, first = -1, sum = 0, best_step = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ best_step = read32(&ch[chn].ao.shu[0].conf[1]) &</span><br><span style="color: hsl(120, 100%, 40%);">+ (SHU_CONF1_DATLAT_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, best_step);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_init(chn, rank, 0x400, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (datlat = datlat_begin; datlat < DATLAT_TAP_NUMBER; datlat++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dle_factor_handler(chn, datlat);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (err && (first != -1))</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sum > 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (err == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (first == -1)</span><br><span style="color: hsl(120, 100%, 40%);">+ first = datlat;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sum++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("TAP=%2d, err_value=0x%8x, sum=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ datlat, err, sum);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.dummy_rd, dummy_rd_backup);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ best_step = first + (sum >> 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("first_step=%d, total pass=%d, best_step=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ first, sum, best_step);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(sum != 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dle_factor_handler(chn, best_step);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << PADCTRL_DQIENQKEND_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (u8)best_step;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 datlat0, u8 datlat1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 final_datlat = MAX(datlat0, datlat1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dle_factor_handler(chn, final_datlat);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[%s] RK0: %d, RK1: %d, Final_Datlat %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, datlat0, datlat1, final_datlat);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void dramc_rx_dqs_gating_post_process(u8 chn)</span><br><span> {</span><br><span> u8 dqs, rank_rx_dvs, dqsinctl, rank;</span><br><span>@@ -1801,6 +1876,7 @@</span><br><span> </span><br><span> void dramc_calibrate_all_channels(const struct sdram_params *pams)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rx_datlat[RANK_MAX] = {0x0};</span><br><span> for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {</span><br><span> for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {</span><br><span> dramc_show("start K ch:%d, rank:%d\n", chn, rk);</span><br><span>@@ -1812,9 +1888,11 @@</span><br><span> dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams);</span><br><span> dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams);</span><br><span> dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams);</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk);</span><br><span> dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams);</span><br><span> }</span><br><span> </span><br><span> dramc_rx_dqs_gating_post_process(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dual_rank_rx_datlat_cal(chn, rx_datlat[0], rx_datlat[1]);</span><br><span> }</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28843">change 28843</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97 </div>
<div style="display:none"> Gerrit-Change-Number: 28843 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>