<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28838">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add DDR driver of pre-calibration part<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br> patches.<br><br>Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61<br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/Makefile.inc<br>A src/soc/mediatek/mt8183/dramc_pi_calibration_api.c<br>M src/soc/mediatek/mt8183/emi.c<br>M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h<br>4 files changed, 213 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/28838/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index e9b5f42..ec2a9c0 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -22,6 +22,7 @@</span><br><span> </span><br><span> romstage-y += ../common/cbmem.c emi.c</span><br><span> romstage-y += dramc_pi_basic_api.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += dramc_pi_calibration_api.c</span><br><span> romstage-y += memory.c</span><br><span> romstage-y += ../common/gpio.c gpio.c</span><br><span> romstage-y += ../common/mmu_operations.c mmu_operations.c</span><br><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c5ec9c7</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>@@ -0,0 +1,205 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_register.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_pi_api.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_read_dbi_onoff(u8 onoff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ onoff << SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_write_dbi_onoff(u8 onoff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].wodt,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_WODT_DBIWR_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ onoff << SHU1_WODT_DBIWR_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dramc_phy_dcm_2_channel(u8 chn, u8 en)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!en) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 20) | (0x1 << 19) | 0x3FF << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 20) | (0x1 << 19) | 0x3FF << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[0].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1FFF << 19);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[1].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1FFF << 19);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[shu].ca_cmd[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1FFF << 19);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.misc_cg_ctrl5,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_enable_phy_dcm(u8 en)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 broadcast_bak = dramc_get_broadcast();</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_MAX ; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[0].dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[1].dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].ca_dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((en ? 0x1 : 0) << 2) | ((en ? 0 : 0x1) << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((en ? 0 : 0x1) << 26) | ((en ? 0x1 : 0) << 30) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((en ? 0x1 : 0) << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DCM on :CHANNEL_EMI free run ; DCM off :mem_dcm */</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(en == 0 || en == 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033E | (0x40 << en));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033F | (0x40 << en));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033E | (0x40 << en));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26,</span><br><span style="color: hsl(120, 100%, 40%);">+ (en ? 0 : 0x3) << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[shu].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x7 << 17, (en ? 0x7 : 0) << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[shu].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x7 << 17, (en ? 0x7 : 0) << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[shu].ca_cmd[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x7 << 17, (en ? 0x7 : 0) << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_dramc_phy_dcm_2_channel(chn, en);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_broadcast(broadcast_bak);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void reset_delay_chain_before_calibration(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 rank = 0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xffffff << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xfffffff << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xfffffff << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xf << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xf << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_hw_gating_onoff(u8 chn, u8 onoff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14,</span><br><span style="color: hsl(120, 100%, 40%);">+ (onoff << 14) | (onoff << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28, onoff << 28);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 24, onoff << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 22, onoff << 22);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 delay = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[5], 0x7 << 20, delay << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[5], 0x7 << 20, delay << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 13), (0x0 << 12) | (0x0 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 13), (0x0 << 12) | (0x0 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_apply_pre_calibration_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shu = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_enable_phy_dcm(0);</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_delay_chain_before_calibration();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 25);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_write_dbi_onoff(DBI_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_read_dbi_onoff(DBI_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int chn = 0; chn < CHANNEL_MAX; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_gating_onoff(chn, GATING_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_input_delay_tracking_init_by_freq(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 28) | (0x1 << 23) | (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c</span><br><span>index 37997aa..ba913a2 100644</span><br><span>--- a/src/soc/mediatek/mt8183/emi.c</span><br><span>+++ b/src/soc/mediatek/mt8183/emi.c</span><br><span>@@ -293,7 +293,13 @@</span><br><span> emi_init2(params);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void do_calib(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_apply_pre_calibration_config();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void mt_set_emi(const struct sdram_params *params)</span><br><span> {</span><br><span> init_dram(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ do_calib(params);</span><br><span> }</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>index af96316..ed9eb81 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>@@ -138,4 +138,5 @@</span><br><span> void dramc_set_broadcast(u32 onoff);</span><br><span> u32 dramc_get_broadcast(void);</span><br><span> void dramc_sw_impedance(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_apply_pre_calibration_config(void);</span><br><span> #endif /* _DRAMC_PI_API_MT8183_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28838">change 28838</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28838"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 </div>
<div style="display:none"> Gerrit-Change-Number: 28838 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>