<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28857">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_PACKAGE_THERM_INTERRUPT to x86/msr.h<br><br>Change-Id: I738c337c7eed9be6c1ae6dcc03c60af399f83196<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/cannonlake/include/soc/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/skylake/include/soc/msr.h<br>10 files changed, 1 insertion(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28857/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index 46c7a65..470c6ba 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -26,7 +26,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 5d9b8d3..c23a87e 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 97c1abe..b718616 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -41,7 +41,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index aeb113a..c4ca738 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 2f28799..0ad2329 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -26,7 +26,6 @@</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 9148349..77b6b4b 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #define IA32_MISC_ENABLE 0x1a0</span><br><span> /* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */</span><br><span> #define BURST_MODE_DISABLE (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_IA32_PAT 0x277</span><br><span> #define IA32_BIOS_UPDT_TRIG 0x79</span><br><span> #define IA32_BIOS_SIGN_ID 0x8b</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 40a9340..0bdf29e 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -33,7 +33,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRRphysBase_MSR 0x1f4</span><br><span> #define EMRRphysMask_MSR 0x1f5</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>index f8a342c..c85def4 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f9</span><br><span> #define MSR_VR_MISC_CONFIG2 0x636</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 58d4cfe..73c5675 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -35,7 +35,6 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRR_PHYS_BASE_MSR 0x1f4</span><br><span> #define EMRR_PHYS_MASK_MSR 0x1f5</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index a371e47..a1bb0fc 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -24,7 +24,6 @@</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28857">change 28857</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I738c337c7eed9be6c1ae6dcc03c60af399f83196 </div>
<div style="display:none"> Gerrit-Change-Number: 28857 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>