<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28865">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL<br><br>TEST=Build Grunt<br>BUG=b:77602074<br><br>Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl<br>1 file changed, 38 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28865/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl</span><br><span>index a639260..15e4d2f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl</span><br><span>@@ -188,6 +188,7 @@</span><br><span> </span><br><span> OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)</span><br><span> Field( SMIC, ByteAcc, NoLock, Preserve) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MISC registers */</span><br><span> offset (0x03ee),</span><br><span> U3PS, 2, /* Usb3PowerSel */</span><br><span> </span><br><span>@@ -197,6 +198,7 @@</span><br><span> U2RP, 1, /* Usb2 Ref Clock Powerdown */</span><br><span> U3RP, 1, /* Usb3 Ref Clock Powerdown */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* XHCI_PM registers */</span><br><span> offset (0x1c00),</span><br><span> , 1,</span><br><span> ,6,</span><br><span>@@ -217,70 +219,71 @@</span><br><span> offset (0x1c08),</span><br><span> UA08, 32,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e4a),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* AOAC Registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e4a), /* I2C0 D3 Control */</span><br><span> I0TD, 2,</span><br><span> , 1,</span><br><span> I0PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e4b),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e4b), /* I2C0 D3 State */</span><br><span> I0DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e4c),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e4c), /* I2C1 D3 Control */</span><br><span> I1TD, 2,</span><br><span> , 1,</span><br><span> I1PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e4d),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e4d), /* I2C1 D3 State */</span><br><span> I1DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e4e),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e4e), /* I2C2 D3 Control */</span><br><span> I2TD, 2,</span><br><span> , 1,</span><br><span> I2PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e4f),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e4f), /* I2C2 D3 State */</span><br><span> I2DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e50),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e50), /* I2C3 D3 Control */</span><br><span> I3TD, 2,</span><br><span> , 1,</span><br><span> I3PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e51),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e51), /* I2C3 D3 State */</span><br><span> I3DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e56),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e56), /* UART0 D3 Control */</span><br><span> U0TD, 2,</span><br><span> , 1,</span><br><span> U0PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e57),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e57), /* UART0 D3 State */</span><br><span> U0DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e58),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e58), /* UART1 D3 Control */</span><br><span> U1TD, 2,</span><br><span> , 1,</span><br><span> U1PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e59),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e59), /* UART1 D3 State */</span><br><span> U1DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e5e),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e5e), /* SATA D3 Control */</span><br><span> SATD, 2,</span><br><span> , 1,</span><br><span> SAPD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e5f),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e5f), /* SATA D3 State */</span><br><span> SADS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e64),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e64), /* USB2 D3 Control */</span><br><span> U2TD, 2,</span><br><span> , 1,</span><br><span> U2PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e65),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e65), /* USB2 D3 State */</span><br><span> U2DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e6e),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e6e), /* USB3 D3 Control */</span><br><span> U3TD, 2,</span><br><span> , 1,</span><br><span> U3PD, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e6f),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e6f), /* USB3 D3 State */</span><br><span> U3DS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e70),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e70), /* SD D3 Control */</span><br><span> SDTD, 2,</span><br><span> , 1,</span><br><span> , 1,</span><br><span>@@ -288,10 +291,10 @@</span><br><span> SDRT, 1,</span><br><span> SDSC, 1,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e71),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e71), /* SD D3 State */</span><br><span> SDDS, 3,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e80),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e80), /* Shadow Register Request */</span><br><span> , 15,</span><br><span> RQ15, 1,</span><br><span> , 2,</span><br><span>@@ -301,7 +304,7 @@</span><br><span> RQ24, 1,</span><br><span> , 5,</span><br><span> RQTY, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1e84),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1e84), /* Shadow Register Status */</span><br><span> , 15,</span><br><span> SASR, 1, /* SATA 15 Shadow Reg Request Status Register */</span><br><span> , 2,</span><br><span>@@ -310,13 +313,13 @@</span><br><span> U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */</span><br><span> SDSR, 1, /* SD 24 Shadow Reg Request Status Register */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1ea0),</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1ea0), /* PwrGood Control */</span><br><span> PG1A, 1,</span><br><span> PG2_, 1,</span><br><span> ,1,</span><br><span> U3PG, 1, /* Usb3 Power Good BIT3 */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- offset (0x1ea3), /* Power Good Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ offset (0x1ea3), /* PwrGood Control b[31:24] */</span><br><span> PGA3, 8 ,</span><br><span> }</span><br><span> </span><br><span>@@ -324,35 +327,35 @@</span><br><span> Field(FCFG, DwordAcc, NoLock, Preserve)</span><br><span> {</span><br><span> /* XHCI */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00080010),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00080010), /* Base address */</span><br><span> XHBA, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x0008002c),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x0008002c), /* Subsystem ID / Vendor ID */</span><br><span> XH2C, 32,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00080048),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00080048), /* Indirect PCI Index Register */</span><br><span> IDEX, 32,</span><br><span> DATA, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00080054),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00080054), /* PME Control / Status */</span><br><span> U_PS, 2,</span><br><span> </span><br><span> /* EHCI */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00090004),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00090004), /* Control */</span><br><span> , 1,</span><br><span> EHME, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00090010),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00090010), /* Base address */</span><br><span> EHBA, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x0009002c),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x0009002c), /* Subsystem ID / Vendor ID */</span><br><span> EH2C, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00090054),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00090054), /* EHCI Spare 1 */</span><br><span> EH54, 8,</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x00090064),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x00090064), /* Misc Control 2 */</span><br><span> EH64, 8,</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000900c4),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x000900c4), /* PME Control / Status */</span><br><span> E_PS, 2,</span><br><span> </span><br><span> /* LPC Bridge */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x000a30cb),</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x000a30cb), /* ClientRomProtect[31:24] */</span><br><span> , 7,</span><br><span> AUSS, 1, /* AutoSizeStart */</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28865">change 28865</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2 </div>
<div style="display:none"> Gerrit-Change-Number: 28865 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>