<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28840">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add DDR driver of write leveling part<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br>     patches.<br><br>Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56<br>Signed-off-by: Huayang Duan <huayang.duan@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c<br>1 file changed, 27 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28840/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>index 0542baa..7b42287 100644</span><br><span>--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>@@ -83,6 +83,31 @@</span><br><span>    clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_write_leveling(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+           const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER])</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+      s32 clock_delay_max = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+    dramc_show("chn:%d, rank:%d params write level:0x%x, 0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+               chn, rank, wr_level[chn][rank][0], wr_level[chn][rank][1]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],</span><br><span style="color: hsl(120, 100%, 40%);">+           SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+              clock_delay_max << SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+              s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+         assert(wrlevel_dq_delay < 0x40);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+         clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+                  FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+                   FINE_TUNE_DQ_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+                    (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+                     (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+                     (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+      }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void cmd_bus_training(u8 chn, u8 rank,</span><br><span>              const struct sdram_params *params)</span><br><span> {</span><br><span>@@ -292,6 +317,8 @@</span><br><span>                        dramc_show("start K ch:%d, rank:%d\n", chn, rk);</span><br><span>                   auto_refresh_switch(chn, 0);</span><br><span>                         cmd_bus_training(chn, rk, pams);</span><br><span style="color: hsl(120, 100%, 40%);">+                      dramc_write_leveling(chn, rk, pams->wr_level);</span><br><span style="color: hsl(120, 100%, 40%);">+                     auto_refresh_switch(chn, 1);</span><br><span>                 }</span><br><span>    }</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28840">change 28840</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28840"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56 </div>
<div style="display:none"> Gerrit-Change-Number: 28840 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>