<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28799">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices<br><br>This patch provides option for PCI IRQ mapping in both PIC and APIC mode.<br><br>TEST=Build and Boot on CNL RVP.<br><br>Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A src/soc/intel/cannonlake/acpi/irqlinks.asl<br>M src/soc/intel/cannonlake/acpi/pci_irqs.asl<br>M src/soc/intel/cannonlake/acpi/southbridge.asl<br>M src/soc/intel/cannonlake/include/soc/irq.h<br>4 files changed, 417 insertions(+), 85 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/28799/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi/irqlinks.asl b/src/soc/intel/cannonlake/acpi/irqlinks.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..0403ea0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/irqlinks.asl</span><br><span>@@ -0,0 +1,282 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PIRQ routing control is in PCR ITSS region.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Due to what appears to be an ACPI interpreter bug we do not use</span><br><span style="color: hsl(120, 100%, 40%);">+ * the PCRB() method here as it may not be defined yet because the method</span><br><span style="color: hsl(120, 100%, 40%);">+ * definiton depends on the order of the include files in pch.asl.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * https://bugs.acpica.org/show_bug.cgi?id=1201</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (ITSS, SystemMemory,</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (PCR_ITSS_PIRQA_ROUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ Add (CONFIG_PCR_BASE_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (ITSS, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRA, 8, /* PIRQA Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRB, 8, /* PIRQB Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRC, 8, /* PIRQC Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRD, 8, /* PIRQD Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRE, 8, /* PIRQE Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRF, 8, /* PIRQF Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRG, 8, /* PIRQG Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRH, 8, /* PIRQH Routing Control */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (IREN, 0x80) /* Interrupt Routing Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (IREM, 0x0f) /* Interrupt Routing Mask */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKA)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLA, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLA, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLA)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRA, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLB, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {10}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLB, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLB)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRB, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKC)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLC, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLC, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLC)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRC, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKD)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLD, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLD, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLD)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRD, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKE)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLE, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLE, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLE)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRE, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKF)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLF, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLF, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLF)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRF, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKG)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLG, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLG, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLG)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRG, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (LNKH)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EISAID ("PNP0C0F"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, 8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RTLH, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ IRQ (Level, ActiveLow, Shared) {11}</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ CreateWordField (RTLH, 1, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Zero, IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the bit from PIRQ Routing Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (RTLH)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (And (^^PIRH, ^^IREN)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0x9)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xb)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl</span><br><span>index eeed667..d346ce2 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/pci_irqs.asl</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corp.</span><br><span> * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span>@@ -15,85 +15,127 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Method(_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/irq.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (PICP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* cAVS, SMBus, GbE, Nothpeak */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SerialIo and SCS */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Express Port 9-16 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI Express Port 1-8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* eMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x001AFFFF, 0, 0, eMMC_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SerialIo */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SATA controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0017FFFF, 0, 0, SATA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CSME (HECI, IDE-R, Keyboard and Text redirection */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 2, 0, IDER_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0016FFFF, 3, 0, KT_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SerialIo */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20: xHCI, OTG, SRAM, CNVi WiFi */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 0, 0, XHCI_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 1, 0, OTG_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Integrated Sensor Hub */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0013FFFF, 0, 0, ISH_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Thermal */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Host Bridge */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Root Port D1F0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IGFX Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0002FFFF, 0, 0, IGFX_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA Thermal Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IPU Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0005FFFF, 0, 0, IPU_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA GNA Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0008FFFF, 0, 0, GNA_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (PICN, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D31: cAVS, SMBus, GbE, Nothpeak */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D32: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D29: PCI Express Port 9-16 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D28: PCI Express Port 1-8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D25: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D22: CSME (HECI, IDE-R, KT redirection */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20: xHCI, OTG, SRAM, CNVi WiFi */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19: Can't use PIC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Thermal */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* P.E.G. Root Port D1F0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IGFX Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA Thermal Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA IPU Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SA GNA Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method (_PRT)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Return(Package() {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // PCI Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- // cAVS, SMBus, GbE, Nothpeak</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001FFFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001FFFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001FFFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001FFFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SerialIo and SCS</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001EFFFF, 0, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001EFFFF, 1, 0, 21 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001EFFFF, 2, 0, 22 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001EFFFF, 3, 0, 23 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCI Express Port 9-16</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001DFFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001DFFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001DFFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001DFFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCI Express Port 1-8</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001CFFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001CFFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001CFFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001CFFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // PCI Express Port 17-20</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001BFFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001BFFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001BFFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001BFFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // eMMC</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001AFFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001AFFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001AFFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x001AFFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SerialIo</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0019FFFF, 0, 0, 32 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0019FFFF, 1, 0, 33 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0019FFFF, 2, 0, 34 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SATA controller</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0017FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // CSME (HECI, IDE-R, Keyboard and Text redirection</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0016FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0016FFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0016FFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0016FFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // SerialIo</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0015FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0015FFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0015FFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0015FFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // CNL: D20: xHCI, OTG, CNVi WiFi, SDcard</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0014FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0014FFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0014FFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0014FFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Integrated Sensor Hub</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0013FFFF, 0, 0, 20 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Thermal, UFS, SerialIo SPI 2</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0012FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0012FFFF, 1, 0, 24 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0012FFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0012FFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Host Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- // Root Port D1F0</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0001FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0001FFFF, 1, 0, 17 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0001FFFF, 2, 0, 18 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0001FFFF, 3, 0, 19 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Root Port D1F1</span><br><span style="color: hsl(0, 100%, 40%);">- // Root Port D1F2</span><br><span style="color: hsl(0, 100%, 40%);">- // IGFX Device</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0002FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // Thermal Device</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0004FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // IPU Device</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0005FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- // GNA Device</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0008FFFF, 0, 0, 16 },</span><br><span style="color: hsl(0, 100%, 40%);">- })</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^PICP)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (^PICN)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl</span><br><span>index 6fac398..2b34df5 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi/southbridge.asl</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl</span><br><span>@@ -15,6 +15,13 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/itss.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Interrupt Routing */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqlinks.asl"</span><br><span> </span><br><span> /* PCI IRQ assignment */</span><br><span> #include "pci_irqs.asl"</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h</span><br><span>index 5b6715f..61f4025 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/irq.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/irq.h</span><br><span>@@ -87,8 +87,9 @@</span><br><span> </span><br><span> #define XHCI_IRQ 16</span><br><span> #define OTG_IRQ 17</span><br><span style="color: hsl(0, 100%, 40%);">-#define THRMAL_IRQ 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define CNViWIFI_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_SRAM_IRQ 18</span><br><span style="color: hsl(120, 100%, 40%);">+#define THERMAL_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define CNViWIFI_IRQ 19</span><br><span> #define UFS_IRQ 16</span><br><span> #define CIO_INTA_IRQ 16</span><br><span> #define CIO_INTD_IRQ 19</span><br><span>@@ -101,6 +102,6 @@</span><br><span> </span><br><span> #define IGFX_IRQ 16</span><br><span> #define SA_THERMAL_IRQ 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define SKYCAM_IRQ 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define GMM_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define IPU_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GNA_IRQ 16</span><br><span> #endif /* _SOC_IRQ_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28799">change 28799</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df </div>
<div style="display:none"> Gerrit-Change-Number: 28799 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>