<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28800">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add PCIE ASL entry<br><br>This patch creates _PRT entires for each PCIE root port devices.<br><br>TEST=Able to see PCIE wake device in cat /proc/acpi/wake list<br><br>Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A src/soc/intel/cannonlake/acpi/pcie.asl<br>M src/soc/intel/cannonlake/acpi/southbridge.asl<br>2 files changed, 385 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28800/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..69e16ca</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/pcie.asl</span><br><span>@@ -0,0 +1,382 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Intel PCH PCIe support */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method (IRQM, 1, Serialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQAA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 19 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQAP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQBA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 16 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQBP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQCA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 18 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 17 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQCP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQDA, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, 0, 19 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, 0, 16 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, 0, 17 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, 0, 18 } })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (IQDP, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Switch (ToInteger (Arg0))</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 1, 5, 9, 13 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQAA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQAP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 2, 6, 10, 14 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQBA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQBP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 3, 7, 11, 15 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQCA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQCP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Case (Package () { 4, 8, 12, 16 }) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Default {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IQDP)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP01)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP02)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0001)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP03)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0002)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP04)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0003)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP05)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0004)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP06)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0005)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP07)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0006)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP08)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001C0007)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP09)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP10)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0001)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP11)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0002)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP12)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0003)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP13)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0004)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP14)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0005)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP15)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0006)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP16)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x001D0007)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (RPCS, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ RPPN, 8, /* Root Port Number */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_PRT)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (IRQM (RPPN))</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl</span><br><span>index 2b34df5..ff323c4 100644</span><br><span>--- a/src/soc/intel/cannonlake/acpi/southbridge.asl</span><br><span>+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl</span><br><span>@@ -41,6 +41,9 @@</span><br><span> /* PCH HDA */</span><br><span> #include "pch_hda.asl"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* PCIE Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pcie.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Serial IO */</span><br><span> #include "serialio.asl"</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28800">change 28800</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28800"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 </div>
<div style="display:none"> Gerrit-Change-Number: 28800 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>