<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28786">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Refactor USB code among similar SoCs<br><br>Refactor USB code which will be reused among similar SoCs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Elm<br><br>Change-Id: I06fefb4149a489be991e13ddf624082d11e31765<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>A src/soc/mediatek/common/include/soc/usb_common.h<br>A src/soc/mediatek/common/usb.c<br>M src/soc/mediatek/mt8173/Makefile.inc<br>M src/soc/mediatek/mt8173/include/soc/usb.h<br>M src/soc/mediatek/mt8173/usb.c<br>5 files changed, 351 insertions(+), 293 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28786/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h</span><br><span>new file mode 100644</span><br><span>index 0000000..8a36c6a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/include/soc/usb_common.h</span><br><span>@@ -0,0 +1,172 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_USB_COMMON_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_USB_COMMON_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stddef.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* ip_pw_ctrl0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL0_IP_SW_RST (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* ip_pw_ctrl1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL1_IP_HOST_PDN (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* ip_pw_sts1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define STS1_U3_MAC_RST (0x1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define STS1_SYS125_RST (0x1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define STS1_REF_RST (0x1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define STS1_SYSPLL_STABLE (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* ip_pw_sts2 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define STS2_U2_MAC_RST (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* ip_xhci_cap */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAP_U3_PORT_NUM(p) ((p) & 0xff)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* u3_ctrl_p */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL_U3_PORT_PDN (0x1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL_U3_PORT_DIS (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* u2_ctrl_p */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL_U2_PORT_PDN (0x1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CTRL_U2_PORT_DIS (0x1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct ssusb_ippc_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_pw_ctr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_pw_ctr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_pw_ctr2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_pw_ctr3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_pw_sts1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_pw_sts2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved0[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ip_xhci_cap;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 u3_ctrl_p[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 u2_ctrl_p[6];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U2PHY_COM USBPHYACR5 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U2PHY_COM USBPHYACR6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA6_RG_U2_ISO_EN (0x1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA6_RG_U2_SQTH (0xf << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U2PHY_COM U2PHYACR4 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_USB20_GPIO_MODE (0x1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U2PHY_COM U2PHYDTM0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_UART_EN (0x1 << 26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_DATAIN (0x1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_XCVRSEL (0x1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_SUSPENDM (0x1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_FORCE_TERMSEL (0x1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_DATAIN (0xf << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_DMPULLDOWN (0x1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_DPPULLDOWN (0x1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_XCVRSEL (0x3 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_SUSPENDM (0x1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_TERMSEL (0x1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_DTM0_PART_MASK \</span><br><span style="color: hsl(120, 100%, 40%);">+ (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \</span><br><span style="color: hsl(120, 100%, 40%);">+ P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \</span><br><span style="color: hsl(120, 100%, 40%);">+ P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \</span><br><span style="color: hsl(120, 100%, 40%);">+ P2C_RG_TERMSEL)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U2PHY_COM U2PHYDTM1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_UART_EN (0x1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_VBUSVALID (0x1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_SESSEND (0x1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2C_RG_AVALID (0x1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U3PHYA PHYA_REG0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_U3_VUSB10_ON (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U3PHYA PHYA_REG6 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_TX_EIDLE_CM (0xf << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U3PHYA PHYA_REG9 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_RX_DAC_MUX (0x1f << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U3PHYA_DA REG0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* U3PHYD CDR1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct sif_u2_phy_com {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved0[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usbphyacr5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 usbphyacr6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u2phyacr3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u2phyacr4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[17];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u2phydtm0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u2phydtm1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[36]; /* 0x70 - 0xff */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(sif_u2_phy_com, u2phydtm0, 0x68);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct sif_u3phyd {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved0[23];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 phyd_cdr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[40];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct sif_u3phya {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 phya_reg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved0[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 phya_reg6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 phya_reg9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[54];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct sif_u3phya_da {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved[63];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is defined as weak no-ops that can be overridden by legacy SOCs. Some</span><br><span style="color: hsl(120, 100%, 40%);">+ * legacy SOCs need specific settings before init USB. And we expect future</span><br><span style="color: hsl(120, 100%, 40%);">+ * SOCs will not need it.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_usb_prepare(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void setup_usb_host(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ceeea19</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/common/usb.c</span><br><span>@@ -0,0 +1,174 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/usb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define USBTAG "[SSUSB] "</span><br><span style="color: hsl(120, 100%, 40%);">+#define u3p_msg(fmt, arg...) printk(BIOS_INFO, USBTAG fmt, ##arg)</span><br><span style="color: hsl(120, 100%, 40%);">+#define u3p_err(fmt, arg...) printk(BIOS_ERR, USBTAG fmt, ##arg)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void phy_index_power_on(int index)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct ssusb_sif_port *phy = phy_ports + index;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!index) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* power domain iso disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* switch to USB function. (system register, force ip into usb mode) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!index)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |</span><br><span style="color: hsl(120, 100%, 40%);">+ P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DP/DM BC1.1 path Disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* improve Rx sensitivity */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u2phy.usbphyacr6,</span><br><span style="color: hsl(120, 100%, 40%);">+ PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* OTG Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u3phya_da.reg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u3phya.phya_reg9,</span><br><span style="color: hsl(120, 100%, 40%);">+ P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!index) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* disable Change 100uA current from SSUSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u3phya.phya_reg6,</span><br><span style="color: hsl(120, 100%, 40%);">+ P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u3phyd.phyd_cdr1,</span><br><span style="color: hsl(120, 100%, 40%);">+ P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u3phyd.phyd_cdr1,</span><br><span style="color: hsl(120, 100%, 40%);">+ P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u2phy.u2phydtm1,</span><br><span style="color: hsl(120, 100%, 40%);">+ P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* USB 2.0 slew rate calibration */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&phy->u2phy.usbphyacr5,</span><br><span style="color: hsl(120, 100%, 40%);">+ PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void u3phy_power_on(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t i = 0; i < USB_PORT_NUMBER; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ phy_index_power_on(i);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int check_ip_clk_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int u3_port_num;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 check_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sts1, sts2;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u3_port_num = CAP_U3_PORT_NUM(read32(&ippc_regs->ip_xhci_cap));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ check_bits = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST;</span><br><span style="color: hsl(120, 100%, 40%);">+ check_bits |= (u3_port_num ? STS1_U3_MAC_RST : 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_usecs_expire(&sw, 50000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (stopwatch_expired(&sw)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u3p_err("usb clocks are not stable!!!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sts1 = read32(&ippc_regs->ip_pw_sts1) & check_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+ sts2 = read32(&ippc_regs->ip_pw_sts2) & STS2_U2_MAC_RST;</span><br><span style="color: hsl(120, 100%, 40%);">+ } while ((sts1 != check_bits) || !sts2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int u3phy_ports_enable(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value;</span><br><span style="color: hsl(120, 100%, 40%);">+ int u3_port_num;</span><br><span style="color: hsl(120, 100%, 40%);">+ int u2_port_num;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ value = read32(&ippc_regs->ip_xhci_cap);</span><br><span style="color: hsl(120, 100%, 40%);">+ u3_port_num = CAP_U3_PORT_NUM(value);</span><br><span style="color: hsl(120, 100%, 40%);">+ u2_port_num = CAP_U2_PORT_NUM(value);</span><br><span style="color: hsl(120, 100%, 40%);">+ u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* power on host ip */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* power on and enable all u3 ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < u3_port_num; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,</span><br><span style="color: hsl(120, 100%, 40%);">+ CTRL_U3_PORT_HOST_SEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* power on and enable all u2 ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < u2_port_num; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,</span><br><span style="color: hsl(120, 100%, 40%);">+ CTRL_U2_PORT_HOST_SEL);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return check_ip_clk_status();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void ssusb_soft_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* reset whole ip */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mtk_usb_prepare(void) { /* do nothing */ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void setup_usb_host(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int ret;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u3p_msg("Setting up USB HOST controller...\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtk_usb_prepare();</span><br><span style="color: hsl(120, 100%, 40%);">+ ssusb_soft_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ ret = u3phy_ports_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ret) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u3p_err("%s fail to enable ports\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ u3phy_power_on();</span><br><span style="color: hsl(120, 100%, 40%);">+ u3p_msg("phy power-on done.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>index 73048f4..e125e03 100644</span><br><span>--- a/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8173/Makefile.inc</span><br><span>@@ -80,7 +80,7 @@</span><br><span> ramstage-y += ../common/pll.c pll.c</span><br><span> ramstage-y += rtc.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += usb.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += ../common/usb.c usb.c</span><br><span> </span><br><span> ramstage-y += ddp.c</span><br><span> ramstage-y += dsi.c</span><br><span>diff --git a/src/soc/mediatek/mt8173/include/soc/usb.h b/src/soc/mediatek/mt8173/include/soc/usb.h</span><br><span>index 646b077..8a6f61a 100644</span><br><span>--- a/src/soc/mediatek/mt8173/include/soc/usb.h</span><br><span>+++ b/src/soc/mediatek/mt8173/include/soc/usb.h</span><br><span>@@ -16,147 +16,7 @@</span><br><span> #ifndef SOC_MEDIATEK_MT8173_USB_H</span><br><span> #define SOC_MEDIATEK_MT8173_USB_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* ip_pw_ctrl0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL0_IP_SW_RST (0x1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ip_pw_ctrl1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL1_IP_HOST_PDN (0x1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ip_pw_sts1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define STS1_U3_MAC_RST (0x1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define STS1_SYS125_RST (0x1 << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define STS1_REF_RST (0x1 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define STS1_SYSPLL_STABLE (0x1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ip_pw_sts2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define STS2_U2_MAC_RST (0x1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ip_xhci_cap */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CAP_U3_PORT_NUM(p) ((p) & 0xff)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* u3_ctrl_p */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL_U3_PORT_HOST_SEL (0x1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL_U3_PORT_PDN (0x1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL_U3_PORT_DIS (0x1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* u2_ctrl_p */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL_U2_PORT_HOST_SEL (0x1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL_U2_PORT_PDN (0x1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CTRL_U2_PORT_DIS (0x1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct ssusb_ippc_regs {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_pw_ctr0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_pw_ctr1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_pw_ctr2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_pw_ctr3;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_pw_sts1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_pw_sts2;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved0[3];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 ip_xhci_cap;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved1[2];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 u3_ctrl_p[4];</span><br><span style="color: hsl(0, 100%, 40%);">- u64 u2_ctrl_p[6];</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U2PHY_COM USBPHYACR5 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA5_RG_U2_HSTX_SRCTRL (0x7 << 12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA5_RG_U2_HS_100U_U3_EN (0x1 << 11)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U2PHY_COM USBPHYACR6 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA6_RG_U2_ISO_EN (0x1 << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA6_RG_U2_BC11_SW_EN (0x1 << 23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA6_RG_U2_SQTH (0xf << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U2PHY_COM U2PHYACR4 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_USB20_GPIO_CTL (0x1 << 9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_USB20_GPIO_MODE (0x1 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U2PHY_COM U2PHYDTM0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_UART_EN (0x1 << 26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_DATAIN (0x1 << 23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_DM_PULLDOWN (0x1 << 21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_DP_PULLDOWN (0x1 << 20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_XCVRSEL (0x1 << 19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_SUSPENDM (0x1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_FORCE_TERMSEL (0x1 << 17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_DATAIN (0xf << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_DMPULLDOWN (0x1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_DPPULLDOWN (0x1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_XCVRSEL (0x3 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_SUSPENDM (0x1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_TERMSEL (0x1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_DTM0_PART_MASK \</span><br><span style="color: hsl(0, 100%, 40%);">- (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \</span><br><span style="color: hsl(0, 100%, 40%);">- P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \</span><br><span style="color: hsl(0, 100%, 40%);">- P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \</span><br><span style="color: hsl(0, 100%, 40%);">- P2C_RG_TERMSEL)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U2PHY_COM U2PHYDTM1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_UART_EN (0x1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_VBUSVALID (0x1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_SESSEND (0x1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2C_RG_AVALID (0x1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U3PHYA PHYA_REG0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_U3_VUSB10_ON (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U3PHYA PHYA_REG6 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_TX_EIDLE_CM (0xf << 28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U3PHYA PHYA_REG9 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_RX_DAC_MUX (0x1f << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U3PHYA_DA REG0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_XTAL_EXT_EN_U3 (0x3 << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* U3PHYD CDR1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3D_RG_CDR_BIR_LTD1 (0x1f << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3D_RG_CDR_BIR_LTD0 (0x1f << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct sif_u2_phy_com {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved0[5];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 usbphyacr5;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 usbphyacr6;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 u2phyacr3;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 u2phyacr4;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved1[17];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 u2phydtm0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 u2phydtm1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved2[36]; /* 0x70 - 0xff */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-check_member(sif_u2_phy_com, u2phydtm0, 0x68);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct sif_u3phyd {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved0[23];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 phyd_cdr1;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved1[40];</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct sif_u3phya {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 phya_reg0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved0[5];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 phya_reg6;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved1[2];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 phya_reg9;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved2[54];</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct sif_u3phya_da {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reserved[63];</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/usb_common.h></span><br><span> </span><br><span> struct ssusb_sif_port {</span><br><span> struct sif_u2_phy_com u2phy;</span><br><span>@@ -170,9 +30,9 @@</span><br><span> check_member(ssusb_sif_port, u3phya, 0x300);</span><br><span> check_member(ssusb_sif_port, u3phya_da, 0x400);</span><br><span> check_member(ssusb_sif_port, reserved1, 0x500);</span><br><span style="color: hsl(0, 100%, 40%);">-_Static_assert(sizeof(struct ssusb_sif_port) == 0x800, \</span><br><span style="color: hsl(120, 100%, 40%);">+_Static_assert(sizeof(struct ssusb_sif_port) == 0x800,</span><br><span> "ssusb_sif_port size is wrong!");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void setup_usb_host(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_PORT_NUMBER 2</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/mediatek/mt8173/usb.c b/src/soc/mediatek/mt8173/usb.c</span><br><span>index 1dccfc9..a61a64b 100644</span><br><span>--- a/src/soc/mediatek/mt8173/usb.c</span><br><span>+++ b/src/soc/mediatek/mt8173/usb.c</span><br><span>@@ -13,158 +13,10 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <delay.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/addressmap.h></span><br><span> #include <soc/pll.h></span><br><span> #include <soc/usb.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timer.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define USBTAG "[SSUSB] "</span><br><span style="color: hsl(0, 100%, 40%);">-#define u3p_msg(fmt, arg...) printk(BIOS_INFO, USBTAG fmt, ##arg)</span><br><span style="color: hsl(0, 100%, 40%);">-#define u3p_err(fmt, arg...) printk(BIOS_ERR, USBTAG fmt, ##arg)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">-static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void phy_index_power_on(int index)</span><br><span style="color: hsl(120, 100%, 40%);">+void mtk_usb_prepare(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct ssusb_sif_port *phy = phy_ports + index;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!index) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);</span><br><span style="color: hsl(0, 100%, 40%);">- /* power domain iso disable */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* switch to USB function. (system register, force ip into usb mode) */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!index)</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |</span><br><span style="color: hsl(0, 100%, 40%);">- P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DP/DM BC1.1 path Disable */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- /* improve Rx sensitivity */</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u2phy.usbphyacr6,</span><br><span style="color: hsl(0, 100%, 40%);">- PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));</span><br><span style="color: hsl(0, 100%, 40%);">- /* OTG Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u3phya_da.reg0,</span><br><span style="color: hsl(0, 100%, 40%);">- P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u3phya.phya_reg9,</span><br><span style="color: hsl(0, 100%, 40%);">- P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!index) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* [mt8173]disable Change 100uA current from SSUSB */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u3phya.phya_reg6,</span><br><span style="color: hsl(0, 100%, 40%);">- P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u3phyd.phyd_cdr1,</span><br><span style="color: hsl(0, 100%, 40%);">- P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc));</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u3phyd.phyd_cdr1,</span><br><span style="color: hsl(0, 100%, 40%);">- P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u2phy.u2phydtm1,</span><br><span style="color: hsl(0, 100%, 40%);">- P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* USB 2.0 slew rate calibration */</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&phy->u2phy.usbphyacr5,</span><br><span style="color: hsl(0, 100%, 40%);">- PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void u3phy_power_on(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- phy_index_power_on(0);</span><br><span style="color: hsl(0, 100%, 40%);">- phy_index_power_on(1);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int check_ip_clk_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int u3_port_num;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 check_bits;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 sts1, sts2;</span><br><span style="color: hsl(0, 100%, 40%);">- struct stopwatch sw;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u3_port_num = CAP_U3_PORT_NUM(read32(&ippc_regs->ip_xhci_cap));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- check_bits = STS1_SYSPLL_STABLE | STS1_REF_RST | STS1_SYS125_RST;</span><br><span style="color: hsl(0, 100%, 40%);">- check_bits |= (u3_port_num ? STS1_U3_MAC_RST : 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- stopwatch_init_usecs_expire(&sw, 50000);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- if (stopwatch_expired(&sw)) {</span><br><span style="color: hsl(0, 100%, 40%);">- u3p_err("usb clocks are not stable!!!\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sts1 = read32(&ippc_regs->ip_pw_sts1) & check_bits;</span><br><span style="color: hsl(0, 100%, 40%);">- sts2 = read32(&ippc_regs->ip_pw_sts2) & STS2_U2_MAC_RST;</span><br><span style="color: hsl(0, 100%, 40%);">- } while ((sts1 != check_bits) || !sts2);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int u3phy_ports_enable(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 value;</span><br><span style="color: hsl(0, 100%, 40%);">- int u3_port_num;</span><br><span style="color: hsl(0, 100%, 40%);">- int u2_port_num;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- value = read32(&ippc_regs->ip_xhci_cap);</span><br><span style="color: hsl(0, 100%, 40%);">- u3_port_num = CAP_U3_PORT_NUM(value);</span><br><span style="color: hsl(0, 100%, 40%);">- u2_port_num = CAP_U2_PORT_NUM(value);</span><br><span style="color: hsl(0, 100%, 40%);">- u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* power on host ip */</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* power on and enable all u3 ports */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < u3_port_num; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],</span><br><span style="color: hsl(0, 100%, 40%);">- CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* power on and enable all u2 ports */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < u2_port_num; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],</span><br><span style="color: hsl(0, 100%, 40%);">- CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return check_ip_clk_status();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void ssusb_soft_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* reset whole ip */</span><br><span style="color: hsl(0, 100%, 40%);">- setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);</span><br><span style="color: hsl(0, 100%, 40%);">- clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void setup_usb_host(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int ret;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- u3p_msg("Setting up USB HOST controller...\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> mt_pll_enable_ssusb_clk();</span><br><span style="color: hsl(0, 100%, 40%);">- ssusb_soft_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- ret = u3phy_ports_enable();</span><br><span style="color: hsl(0, 100%, 40%);">- if (ret) {</span><br><span style="color: hsl(0, 100%, 40%);">- u3p_err("%s fail to enable ports\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- u3phy_power_on();</span><br><span style="color: hsl(0, 100%, 40%);">- u3p_msg("phy power-on done.\n");</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28786">change 28786</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I06fefb4149a489be991e13ddf624082d11e31765 </div>
<div style="display:none"> Gerrit-Change-Number: 28786 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>