<p>Sathyanarayana Nujella would like Jairaj Arava and HARSHAPRIYA N to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/28780">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">WIP: mb/google/poppy/variants/nocturne: add dmic cofig params to DT<br><br>DMIC Codec needs minimum clock ON time to function it correctly<br>during switch from sleep-mode to wake-up mode.<br>Hence adding modeswitch_delay_ms as per DMIC spec.<br><br>BUG=b:112888584<br>TEST=Verified DT entry has modeswitch_delay_ms<br><br>Change-Id: Iabf1d2329880d7e247efac00d2160606792dab00<br>Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com><br>Signed-off-by: Jairaj Arava <jairaj.arava@intel.com><br>Signed-off-by: Harsha Priya <harshapriya.n@intel.com><br>---<br>M src/mainboard/google/poppy/variants/nocturne/devicetree.cb<br>1 file changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28780/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>index 70a379c..6c3e007 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>@@ -434,6 +434,10 @@</span><br><span>                    chip ec/google/chromeec</span><br><span>                              device pnp 0c09.0 on end</span><br><span>                     end</span><br><span style="color: hsl(120, 100%, 40%);">+                   chip drivers/generic/dmic</span><br><span style="color: hsl(120, 100%, 40%);">+                             register "modeswitch_delay_ms" = "35"</span><br><span style="color: hsl(120, 100%, 40%);">+                             device generic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+                       end</span><br><span>          end # LPC Interface</span><br><span>          device pci 1f.1 on  end # P2SB</span><br><span>               device pci 1f.2 on  end # Power Management Controller</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28780">change 28780</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28780"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iabf1d2329880d7e247efac00d2160606792dab00 </div>
<div style="display:none"> Gerrit-Change-Number: 28780 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Jairaj Arava <jairaj.arava@intel.com> </div>