<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28764">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Make gnvs ASL whitespace consistent<br><br>The globalnvs.asl file had become mixed with tabs and spaces to align<br>columns.  Use all tabs to align the comments.<br><br>BUG=b:BUG=b:77602074<br><br>Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/globalnvs.asl<br>1 file changed, 13 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28764/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>index 7e696aa..ba50e38 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>@@ -28,19 +28,19 @@</span><br><span> {</span><br><span>       /* Miscellaneous */</span><br><span>  Offset (0x00),</span><br><span style="color: hsl(0, 100%, 40%);">-  PCNT,   8,      // 0x00 - Processor Count</span><br><span style="color: hsl(0, 100%, 40%);">-       PPCM,   8,      // 0x01 - Max PPC State</span><br><span style="color: hsl(0, 100%, 40%);">- LIDS,   8,      // 0x02 - LID State</span><br><span style="color: hsl(0, 100%, 40%);">-     PWRS,   8,      // 0x03 - AC Power State</span><br><span style="color: hsl(0, 100%, 40%);">-        DPTE,   8,      // 0x04 - Enable DPTF</span><br><span style="color: hsl(0, 100%, 40%);">-   CBMC,   32,     // 0x05 - 0x08 - coreboot Memory Console</span><br><span style="color: hsl(0, 100%, 40%);">-        PM1I,   64,     // 0x09 - 0x10 - System Wake Source - PM1 Index</span><br><span style="color: hsl(0, 100%, 40%);">- GPEI,   64,     // 0x11 - 0x18 - GPE Wake Source</span><br><span style="color: hsl(0, 100%, 40%);">-        NHLA,   64,     // 0x19 - 0x20 - NHLT Address</span><br><span style="color: hsl(0, 100%, 40%);">-   NHLL,   32,     // 0x21 - 0x24 - NHLT Length</span><br><span style="color: hsl(0, 100%, 40%);">-    PRT0,   32,     // 0x25 - 0x28 - PERST_0 Address</span><br><span style="color: hsl(0, 100%, 40%);">-        SCDP,   8,      // 0x29 - SD_CD GPIO portid</span><br><span style="color: hsl(0, 100%, 40%);">-     SCDO,   8,      // 0x2A - GPIO pad offset relative to the community</span><br><span style="color: hsl(120, 100%, 40%);">+   PCNT,   8,      // 0x00 - Processor Count</span><br><span style="color: hsl(120, 100%, 40%);">+     PPCM,   8,      // 0x01 - Max PPC State</span><br><span style="color: hsl(120, 100%, 40%);">+       LIDS,   8,      // 0x02 - LID State</span><br><span style="color: hsl(120, 100%, 40%);">+   PWRS,   8,      // 0x03 - AC Power State</span><br><span style="color: hsl(120, 100%, 40%);">+      DPTE,   8,      // 0x04 - Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ CBMC,   32,     // 0x05 - 0x08 - coreboot Memory Console</span><br><span style="color: hsl(120, 100%, 40%);">+      PM1I,   64,     // 0x09 - 0x10 - System Wake Source - PM1 Index</span><br><span style="color: hsl(120, 100%, 40%);">+       GPEI,   64,     // 0x11 - 0x18 - GPE Wake Source</span><br><span style="color: hsl(120, 100%, 40%);">+      NHLA,   64,     // 0x19 - 0x20 - NHLT Address</span><br><span style="color: hsl(120, 100%, 40%);">+ NHLL,   32,     // 0x21 - 0x24 - NHLT Length</span><br><span style="color: hsl(120, 100%, 40%);">+  PRT0,   32,     // 0x25 - 0x28 - PERST_0 Address</span><br><span style="color: hsl(120, 100%, 40%);">+      SCDP,   8,      // 0x29 - SD_CD GPIO portid</span><br><span style="color: hsl(120, 100%, 40%);">+   SCDO,   8,      // 0x2A - GPIO pad offset relative to the community</span><br><span>  TMPS,   8,      // 0x2B - Temperature Sensor ID</span><br><span>      TLVL,   8,      // 0x2C - Throttle Level Limit</span><br><span>       FLVL,   8,      // 0x2D - Current FAN Level</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28764">change 28764</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28764"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 </div>
<div style="display:none"> Gerrit-Change-Number: 28764 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>