<p>Werner Zeh <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/28735">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Werner Zeh: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl1: Add new mainboard variant mc_apl2<br><br>This mainboard is based on mc_apl1. In a first step, it contains a copy<br>of mc_apl1 directory with minimum changes. Special adaptations for<br>mc_apl2 mainboard will follow in separate commits.<br><br>Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>Reviewed-on: https://review.coreboot.org/28735<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Werner Zeh <werner.zeh@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/Kconfig<br>M src/mainboard/siemens/mc_apl1/Kconfig.name<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb<br>A src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c<br>6 files changed, 197 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>index 97ba66f..783207c 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/Kconfig</span><br><span>@@ -17,10 +17,12 @@</span><br><span> config VARIANT_DIR</span><br><span> string</span><br><span> default "mc_apl1" if BOARD_SIEMENS_MC_APL1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "mc_apl2" if BOARD_SIEMENS_MC_APL2</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "MC APL1" if BOARD_SIEMENS_MC_APL1</span><br><span style="color: hsl(120, 100%, 40%);">+ default "MC APL2" if BOARD_SIEMENS_MC_APL2</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>index 112bbb3..7f5f263 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/Kconfig.name</span><br><span>@@ -1,3 +1,7 @@</span><br><span> config BOARD_SIEMENS_MC_APL1</span><br><span style="color: hsl(0, 100%, 40%);">- bool "MC APL1"</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> MC APL1"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SIEMENS_MC_APL2</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> MC APL2"</span><br><span> select BOARD_SIEMENS_BASEBOARD_MC_APL1</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..aa90041</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig</span><br><span>@@ -0,0 +1,14 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_SIEMENS_MC_APL2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SIEMENS_MC_APL2_VAR</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVER_INTEL_I210</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_RX6110SA</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVER_SIEMENS_NC_FPGA</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/mc_apl2/devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_SIEMENS_MC_APL2</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..f3c87b2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..42c4310</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb</span><br><span>@@ -0,0 +1,109 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sci_irq" = "SCIS_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "serirq_mode" = "SERIRQ_CONTINUOUS"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Disable all clkreq of PCIe root ports as SMARC interface do not</span><br><span style="color: hsl(120, 100%, 40%);">+ # have this pins.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for HS400, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR104/HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl1" = "0x0C16"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC TX DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_tx_data_cntl2" = "0x28162828"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl1" = "0x00181717"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EMMC RX CMD/DATA Delay 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # Refer to EDS-Vol2-22.3.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [17:16] stands for Rx Clock before Output Buffer</span><br><span style="color: hsl(120, 100%, 40%);">+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ # [6:0] steps of delay for HS200, each 125ps.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_rx_cmd_data_cntl2" = "0x10008"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0:HS400(Default), 1:HS200, 2:DDR50</span><br><span style="color: hsl(120, 100%, 40%);">+ register "emmc_host_max_speed" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # - Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.1 off end # - DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.2 off end # - NPK</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # - Gen - Display</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 off end # - Iunit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end # - P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.1 off end # - PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.2 on end # - SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.3 off end # - Shared SRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 off end # - Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # - ISH</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # - SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # - RP 2 - PCIe A 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.1 on end # - RP 3 - PCIe A 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.2 on end # - RP 4 - PCIe-A 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.3 on end # - RP 5 - PCIe-A 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # - RP 0 - PCIe-B 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 on end # - RP 1 - PCIe-B 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # - XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # - XDCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # - I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable external RTC chip</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/rx6110sa</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pmon_sampling" = "PMON_SAMPL_256_MS"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bks_on" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bks_off" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "iocut_en" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "set_user_date" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_year" = "04"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_month" = "07"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_day" = "01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "user_weekday" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 0x32 on end # RTC RX6110 SA</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 on end # - I2C 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 on end # - I2C 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on end # - I2C 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # - I2C 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.1 on end # - I2C 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.2 on end # - I2C 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.3 on end # - I2C 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # - UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end # - UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # - UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end # - UART 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # - SPI 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # - SPI 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 off end # - SPI 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 off end # - PWM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # - SDCARD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # - eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # - UFS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # - SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # - LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # - SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0c2418a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c</span><br><span>@@ -0,0 +1,66 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hwilib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_mainboard_final(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t cmd = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Master Enable for on-board PCI device. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd = pci_read_config16(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd |= PCI_COMMAND_MASTER;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(dev, PCI_COMMAND, cmd);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void wait_for_legacy_dev(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t legacy_delay, us_since_boot;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct stopwatch sw;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Open main hwinfo block. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get legacy delay parameter from hwinfo. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(legacy_delay)) != sizeof(legacy_delay))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ us_since_boot = get_us_since_boot();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No need to wait if the time since boot is already long enough.*/</span><br><span style="color: hsl(120, 100%, 40%);">+ if (us_since_boot > legacy_delay)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...",</span><br><span style="color: hsl(120, 100%, 40%);">+ legacy_delay - us_since_boot, legacy_delay);</span><br><span style="color: hsl(120, 100%, 40%);">+ stopwatch_wait_until_expired(&sw);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "done!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28735">change 28735</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb </div>
<div style="display:none"> Gerrit-Change-Number: 28735 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>