<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28766">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add USB settings to gnvs<br><br>A later patch will rely on two USB settings from the BIOS.  Add these<br>to the global_gnvs_t structure.<br><br>The first is a data that will be used to locate the xHCI firmware for<br>reloading after a resume.  Although the existing calculations will be<br>somewhat simple, keeping this on the coreboot side will help in the<br>event multiple FWs are eventually in the build.<br><br>The second item is a usable EHCI base address that may be programmed<br>during S3 suspend and resume.  At the time the PTS and WAK code runs,<br>the BAR will be clear.<br><br>BUG=b:77602074<br><br>Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/globalnvs.asl<br>M src/soc/amd/stoneyridge/include/soc/nvs.h<br>2 files changed, 11 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28766/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>index f77d108..6d38d6b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>@@ -65,6 +65,11 @@</span><br><span>   , 2,</span><br><span>         ESPI,   1,      //        ESPI, 27</span><br><span>   , 4,</span><br><span style="color: hsl(120, 100%, 40%);">+  FW00,   16,     // 0x35 - xHCI FW ROM addr, boot RAM</span><br><span style="color: hsl(120, 100%, 40%);">+  FW01,   32,     // 0x37 - xHCI FW RAM addr, boot RAM</span><br><span style="color: hsl(120, 100%, 40%);">+  FW02,   16,     // 0x3B - xHCI FW ROM addr, Instruction RAM</span><br><span style="color: hsl(120, 100%, 40%);">+   FW03,   32,     // 0x3D - xHCI FW RAM addr, Instruction RAM</span><br><span style="color: hsl(120, 100%, 40%);">+   EH10,   32,     // 0x41 - EHCI BAR</span><br><span>   /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */</span><br><span>         Offset (0x100),</span><br><span>      #include <vendorcode/google/chromeos/acpi/gnvs.asl></span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>index 667f6ef..8fa3236 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>@@ -52,7 +52,12 @@</span><br><span>      uint8_t         tpsv; /* 0x2F - Passive Threshold */</span><br><span>         uint8_t         tmax; /* 0x30 - CPU Tj_max */</span><br><span>        aoac_devs_t     aoac; /* 0x31 - AOAC device enables */</span><br><span style="color: hsl(0, 100%, 40%);">-  uint8_t         unused[203];</span><br><span style="color: hsl(120, 100%, 40%);">+  uint16_t        fw00; /* 0x35 - XhciFwRomAddr_Rom, Boot RAM */</span><br><span style="color: hsl(120, 100%, 40%);">+        uint32_t        fw01; /* 0x37 - XhciFwRamAddr_Rom, Boot RAM sz/base */</span><br><span style="color: hsl(120, 100%, 40%);">+        uint16_t        fw02; /* 0x3B - XhciFwRomAddr_Ram, Instr RAM */</span><br><span style="color: hsl(120, 100%, 40%);">+       uint32_t        fw03; /* 0x3D - XhciFwRomAddr_Ram, Instr RAM sz/base */</span><br><span style="color: hsl(120, 100%, 40%);">+       uint32_t        eh10; /* 0x41 - EHCI BAR */</span><br><span style="color: hsl(120, 100%, 40%);">+   uint8_t         unused[187];</span><br><span> </span><br><span>     /* ChromeOS specific (0x100 - 0xfff) */</span><br><span>      chromeos_acpi_t chromeos;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28766">change 28766</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28766"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb </div>
<div style="display:none"> Gerrit-Change-Number: 28766 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>