<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28765">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Create gnvs entries for AOAC devices<br><br>A later patch will leverage AMD's ASL support for handling AOAC<br>devices. This will gather coreboot's device enables from a bitwise field,<br>where each bit corresponds to the register offset used to control<br>each devices.<br><br>Create an identical structure, and add it to the nvs ASL and global_nvs_t<br>structure.<br><br>BUG=b:77602074<br><br>Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/acpi/globalnvs.asl<br>M src/soc/amd/stoneyridge/include/soc/nvs.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>3 files changed, 42 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28765/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>index ba50e38..f77d108 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl</span><br><span>@@ -47,6 +47,24 @@</span><br><span> TCRT, 8, // 0x2E - Critical Threshold</span><br><span> TPSV, 8, // 0x2F - Passive Threshold</span><br><span> TMAX, 8, // 0x30 - CPU Tj_max</span><br><span style="color: hsl(120, 100%, 40%);">+ , 5, // 0x31 - AOAC Device Enables</span><br><span style="color: hsl(120, 100%, 40%);">+ IC0E, 1, // I2C0, 5</span><br><span style="color: hsl(120, 100%, 40%);">+ IC1E, 1, // I2C1, 6</span><br><span style="color: hsl(120, 100%, 40%);">+ IC2E, 1, // I2C2, 7</span><br><span style="color: hsl(120, 100%, 40%);">+ IC3E, 1, // I2C3, 8</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ UT0E, 1, // UART0, 11</span><br><span style="color: hsl(120, 100%, 40%);">+ UT1E, 1, // UART1, 12</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ ST_E, 1, // SATA, 15</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ EHCE, 1, // EHCI, 18</span><br><span style="color: hsl(120, 100%, 40%);">+ , 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ XHCE, 1, // XCHI, 23</span><br><span style="color: hsl(120, 100%, 40%);">+ SD_E, 1, // SD, 24</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ ESPI, 1, // ESPI, 27</span><br><span style="color: hsl(120, 100%, 40%);">+ , 4,</span><br><span> /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */</span><br><span> Offset (0x100),</span><br><span> #include <vendorcode/google/chromeos/acpi/gnvs.asl></span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>index bcac3a9..667f6ef 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h</span><br><span>@@ -28,6 +28,7 @@</span><br><span> #include <compiler.h></span><br><span> #include <stdint.h></span><br><span> #include <vendorcode/google/chromeos/gnvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/southbridge.h></span><br><span> </span><br><span> typedef struct global_nvs_t {</span><br><span> /* Miscellaneous */</span><br><span>@@ -50,7 +51,8 @@</span><br><span> uint8_t tcrt; /* 0x2E - Critical Threshold */</span><br><span> uint8_t tpsv; /* 0x2F - Passive Threshold */</span><br><span> uint8_t tmax; /* 0x30 - CPU Tj_max */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t unused[207];</span><br><span style="color: hsl(120, 100%, 40%);">+ aoac_devs_t aoac; /* 0x31 - AOAC device enables */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t unused[203];</span><br><span> </span><br><span> /* ChromeOS specific (0x100 - 0xfff) */</span><br><span> chromeos_acpi_t chromeos;</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index f054b3b..3239842 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -400,6 +400,27 @@</span><br><span> int status;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct aoac_devs {</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused1:5;</span><br><span style="color: hsl(120, 100%, 40%);">+ int ic0e:1; /* 5: I2C0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ int ic1e:1; /* 6: I2C1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ int ic2e:1; /* 7: I2C2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ int ic3e:1; /* 8: I2C3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused2:2;</span><br><span style="color: hsl(120, 100%, 40%);">+ int ut0e:1; /* 11: UART0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ int ut1e:1; /* 12: UART0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused3:2;</span><br><span style="color: hsl(120, 100%, 40%);">+ int st_e:1; /* 15: SATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused4:2;</span><br><span style="color: hsl(120, 100%, 40%);">+ int ehce:1; /* 18: EHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused5:4;</span><br><span style="color: hsl(120, 100%, 40%);">+ int xhce:1; /* 23: xHCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ int sd_e:1; /* 24: SDIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused6:2;</span><br><span style="color: hsl(120, 100%, 40%);">+ int espi:1; /* 27: ESPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ int unused7:4;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed aoac_devs_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_power_reg {</span><br><span> uint16_t pm1_sts;</span><br><span> uint16_t pm1_en;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28765">change 28765</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 </div>
<div style="display:none"> Gerrit-Change-Number: 28765 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>