<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28752">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move common IA-32 MSRs to "cpu/x86/msr.h"<br><br>Use "cpu/x86/msr.h" for common IA-32 MSRs and correct<br>IA-32 MSRs names.<br><br>Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/common/common_init.c<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/haswell/haswell_init.c<br>M src/cpu/intel/model_1067x/model_1067x_init.c<br>M src/cpu/intel/model_106cx/model_106cx_init.c<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_2065x/model_2065x_init.c<br>M src/cpu/intel/model_206ax/common.c<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/cpu/intel/model_206ax/model_206ax_init.c<br>M src/cpu/intel/model_6ex/model_6ex_init.c<br>M src/cpu/intel/model_6fx/model_6fx_init.c<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/cpu/intel/speedstep/speedstep.c<br>M src/cpu/intel/turbo/turbo.c<br>M src/cpu/via/nano/nano_init.c<br>M src/cpu/via/nano/update_ucode.c<br>M src/cpu/via/nano/update_ucode.h<br>M src/cpu/x86/pae/pgtbl.c<br>M src/cpu/x86/sipi_vector.S<br>M src/include/cpu/intel/l2_cache.h<br>M src/include/cpu/intel/speedstep.h<br>M src/include/cpu/intel/turbo.h<br>M src/include/cpu/x86/msr.h<br>M src/northbridge/intel/nehalem/early_init.c<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/baytrail/include/soc/msr.h<br>M src/soc/intel/baytrail/ramstage.c<br>M src/soc/intel/baytrail/romstage/cache_as_ram.inc<br>M src/soc/intel/baytrail/tsc_freq.c<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/braswell/include/soc/msr.h<br>M src/soc/intel/braswell/ramstage.c<br>M src/soc/intel/braswell/tsc_freq.c<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/cannonlake/cpu.c<br>M src/soc/intel/cannonlake/include/soc/msr.h<br>M src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>M src/soc/intel/common/block/cpu/car/exit_car.S<br>M src/soc/intel/common/block/cpu/cpulib.c<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/common/block/sgx/sgx.c<br>M src/soc/intel/common/block/vmx/vmx.c<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/ramstage.c<br>M src/soc/intel/fsp_baytrail/romstage/report_platform.c<br>M src/soc/intel/fsp_baytrail/tsc_freq.c<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>M src/soc/intel/fsp_broadwell_de/ramstage.c<br>M src/soc/intel/skylake/cpu.c<br>M src/soc/intel/skylake/include/soc/msr.h<br>56 files changed, 127 insertions(+), 260 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28752/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c</span><br><span>index 8dd8559..02eb0e2 100644</span><br><span>--- a/src/cpu/intel/common/common_init.c</span><br><span>+++ b/src/cpu/intel/common/common_init.c</span><br><span>@@ -20,10 +20,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include "common.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void set_vmx(void)</span><br><span> {</span><br><span> struct cpuid_result regs;</span><br><span>@@ -105,7 +101,7 @@</span><br><span> </span><br><span> config->version = version;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_HWP_CAPABILITIES;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_HWP_CAPABILITIES;</span><br><span> </span><br><span> /*</span><br><span> * Highest Performance:</span><br><span>@@ -141,7 +137,7 @@</span><br><span> msr.bit_offset = 8;</span><br><span> config->regs[CPPC_GUARANTEED_PERF] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_HWP_REQUEST;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_HWP_REQUEST;</span><br><span> </span><br><span> /*</span><br><span> * Desired Performance Register:</span><br><span>@@ -182,7 +178,7 @@</span><br><span> */</span><br><span> config->regs[CPPC_COUNTER_WRAP] = unsupported;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_MPERF;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_MPERF;</span><br><span> </span><br><span> /*</span><br><span> * Reference Performance Counter Register:</span><br><span>@@ -192,7 +188,7 @@</span><br><span> msr.bit_offset = 0;</span><br><span> config->regs[CPPC_REF_PERF_COUNTER] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_APERF;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_APERF;</span><br><span> </span><br><span> /*</span><br><span> * Delivered Performance Counter Register:</span><br><span>@@ -200,7 +196,7 @@</span><br><span> */</span><br><span> config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_HWP_STATUS;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_HWP_STATUS;</span><br><span> </span><br><span> /*</span><br><span> * Performance Limited Register:</span><br><span>@@ -210,7 +206,7 @@</span><br><span> msr.bit_offset = 2;</span><br><span> config->regs[CPPC_PERF_LIMITED] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_PM_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_PM_ENABLE;</span><br><span> </span><br><span> /*</span><br><span> * CPPC Enable Register:</span><br><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index e65b370..020b72d 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -20,25 +20,12 @@</span><br><span> /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */</span><br><span> #define SANDYBRIDGE_BCLK 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 87daeac..5dfe016 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -21,25 +21,12 @@</span><br><span> /* Rangeley bus clock is fixed at 100MHz */</span><br><span> #define RANGELEY_BCLK 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_NO_EVICT_MODE 0x2e0</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 8498c1a..4ccb1c1 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -35,25 +35,12 @@</span><br><span> #define HASWELL_BCLK 100</span><br><span> </span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c</span><br><span>index 24de43e..9219839 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell_init.c</span><br><span>+++ b/src/cpu/intel/haswell/haswell_init.c</span><br><span>@@ -649,10 +649,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "haswell: energy policy set to %u\n",</span><br><span> policy);</span><br><span>diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>index 0d9169b..ce5dac4 100644</span><br><span>--- a/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>+++ b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>@@ -190,7 +190,7 @@</span><br><span> </span><br><span> const u32 sub_cstates = cpuid_edx(5);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 3); /* TM1 enable */</span><br><span> if (tm2)</span><br><span> msr.lo |= (1 << 13); /* TM2 enable */</span><br><span>@@ -220,11 +220,11 @@</span><br><span> if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32)))</span><br><span> msr.hi &= ~(1 << (38 - 32));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> if (eist) {</span><br><span> msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>index dd7bbc8..6bf21fd 100644</span><br><span>--- a/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>+++ b/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>@@ -56,7 +56,6 @@</span><br><span> wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> static void configure_misc(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index f87ba77..11d86cd 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -20,26 +20,13 @@</span><br><span> /* Nehalem bus clock is fixed at 133MHz */</span><br><span> #define NEHALEM_BCLK 133</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c</span><br><span>index 322e814..222c2ed 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x_init.c</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x_init.c</span><br><span>@@ -231,10 +231,10 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",</span><br><span> policy);</span><br><span>diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c</span><br><span>index 9775efb..1e832c8 100644</span><br><span>--- a/src/cpu/intel/model_206ax/common.c</span><br><span>+++ b/src/cpu/intel/model_206ax/common.c</span><br><span>@@ -19,8 +19,6 @@</span><br><span> #include <cpu/x86/msr.h></span><br><span> #include "model_206ax.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_ID 0x17</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> int get_platform_id(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 98203b6..f4d469c 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -20,27 +20,12 @@</span><br><span> /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */</span><br><span> #define SANDYBRIDGE_BCLK 100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>index 3cc8d82..194114d 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>@@ -401,10 +401,10 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",</span><br><span> policy);</span><br><span>diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>index 96830c4..8d68b9e 100644</span><br><span>--- a/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>+++ b/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>@@ -58,7 +58,6 @@</span><br><span> wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> static void configure_misc(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span>diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>index a1433f6..9dd1223 100644</span><br><span>--- a/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>+++ b/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>@@ -59,7 +59,6 @@</span><br><span> wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define IA32_PECI_CTL 0x5a0</span><br><span> </span><br><span> static void configure_misc(void)</span><br><span>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>index cf68ecf..7cc2ce1 100644</span><br><span>--- a/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c</span><br><span>@@ -37,10 +37,6 @@</span><br><span> #define G_SMRAME (1 << 3)</span><br><span> #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_CONTROL_LOCK_BIT (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMRR_ENABLE (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> struct ied_header {</span><br><span> char signature[10];</span><br><span> u32 size;</span><br><span>diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c</span><br><span>index 441f2a3..43d5b5a 100644</span><br><span>--- a/src/cpu/intel/speedstep/speedstep.c</span><br><span>+++ b/src/cpu/intel/speedstep/speedstep.c</span><br><span>@@ -72,7 +72,7 @@</span><br><span> msr = rdmsr(MSR_FSB_CLOCK_VCC);</span><br><span> if ((msr.hi & (1 << (63 - 32))) &&</span><br><span> /* supported and */</span><br><span style="color: hsl(0, 100%, 40%);">- !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) {</span><br><span> /* not disabled */</span><br><span> params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask);</span><br><span> params->turbo.is_turbo = 1;</span><br><span>diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c</span><br><span>index 5583c46..c31f4c0 100644</span><br><span>--- a/src/cpu/intel/turbo/turbo.c</span><br><span>+++ b/src/cpu/intel/turbo/turbo.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span> cpuid_regs = cpuid(CPUID_LEAF_PM);</span><br><span> turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);</span><br><span> </span><br><span> if (!turbo_cap && turbo_en) {</span><br><span>@@ -97,9 +97,9 @@</span><br><span> /* Only possible if turbo is available but hidden */</span><br><span> if (get_turbo_state() == TURBO_DISABLED) {</span><br><span> /* Clear Turbo Disable bit in Misc Enables */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.hi &= ~H_MISC_DISABLE_TURBO;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Update cached turbo state */</span><br><span> set_global_turbo_state(TURBO_ENABLED);</span><br><span>@@ -115,9 +115,9 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Set Turbo Disable bit in Misc Enables */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.hi |= H_MISC_DISABLE_TURBO;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Update cached turbo state */</span><br><span> set_global_turbo_state(TURBO_UNAVAILABLE);</span><br><span>diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c</span><br><span>index 62c6316..985a3c7 100644</span><br><span>--- a/src/cpu/via/nano/nano_init.c</span><br><span>+++ b/src/cpu/via/nano/nano_init.c</span><br><span>@@ -28,9 +28,6 @@</span><br><span> #define MODEL_NANO_3000_B0 0x8</span><br><span> #define MODEL_NANO_3000_B2 0xa</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_STATUS 0x00000198</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x00000199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLE 0x000001a0</span><br><span> #define NANO_MYSTERIOUS_MSR 0x120e</span><br><span> </span><br><span> static void nano_finish_fid_vid_transition(void)</span><br><span>@@ -41,7 +38,7 @@</span><br><span> int cnt = 0;</span><br><span> do {</span><br><span> udelay(16);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_PERF_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_PERF_STATUS);</span><br><span> cnt++;</span><br><span> if (cnt > 128) {</span><br><span> printk(BIOS_WARNING,</span><br><span>@@ -61,7 +58,7 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> /* Get voltage and frequency info */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_PERF_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_PERF_STATUS);</span><br><span> u8 min_fid = (msr.hi >> 24);</span><br><span> u8 max_fid = (msr.hi >> 8) & 0xff;</span><br><span> u8 min_vid = (msr.hi >> 16) & 0xff;</span><br><span>@@ -78,7 +75,7 @@</span><br><span> /* Set highest frequency and VID */</span><br><span> msr.lo = msr.hi;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, msr);</span><br><span> /* Wait for the transition to complete, otherwise, the CPU</span><br><span> * might reset itself repeatedly */</span><br><span> nano_finish_fid_vid_transition();</span><br><span>@@ -96,9 +93,9 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> /* Enable Powersaver */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLE, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Enable 6 bit or 7-bit VRM support</span><br><span> * This MSR is not documented by VIA docs, other than setting these</span><br><span>@@ -116,24 +113,24 @@</span><br><span> nano_set_max_fid_vid();</span><br><span> </span><br><span> /* Enable TM3 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= ( (1 << 3) | (1 << 13) );</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLE, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> u8 stepping = ( cpuid_eax(0x1) ) &0xf;</span><br><span> if (stepping >= MODEL_NANO_3000_B0) {</span><br><span> /* Hello Nano 3000. The Terminator needs a CPU upgrade */</span><br><span> /* Enable C1e, C2e, C3e, and C4e states */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */</span><br><span> msr.hi |= (1 << 0); /* C4e */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLE, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> }</span><br><span> </span><br><span> /* Lock on Powersaver */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 20);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLE, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> }</span><br><span> </span><br><span> static void nano_init(struct device *dev)</span><br><span>diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c</span><br><span>index 7c631a6..b8bfd7d 100644</span><br><span>--- a/src/cpu/via/nano/update_ucode.c</span><br><span>+++ b/src/cpu/via/nano/update_ucode.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span> * not the header. The header is just there to help us. */</span><br><span> msr.lo = (unsigned int)(&(ucode->ucode_start));</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_BIOS_UPDT_TRIG, msr);</span><br><span> </span><br><span> /* Let's see if we updated successfully */</span><br><span> msr = rdmsr(MSR_UCODE_UPDATE_STATUS);</span><br><span>diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h</span><br><span>index ef70d23..acf8fdc 100644</span><br><span>--- a/src/cpu/via/nano/update_ucode.h</span><br><span>+++ b/src/cpu/via/nano/update_ucode.h</span><br><span>@@ -18,8 +18,6 @@</span><br><span> </span><br><span> #include <cpu/cpu.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_BIOS_SIGN_ID 0x0000008b</span><br><span> #define MSR_UCODE_UPDATE_STATUS 0x00001205</span><br><span> </span><br><span> #define NANO_UCODE_SIGNATURE 0x53415252</span><br><span>diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c</span><br><span>index cf6bf16..3c1a336 100644</span><br><span>--- a/src/cpu/x86/pae/pgtbl.c</span><br><span>+++ b/src/cpu/x86/pae/pgtbl.c</span><br><span>@@ -184,7 +184,7 @@</span><br><span> msr_t msr;</span><br><span> msr.lo = pat;</span><br><span> msr.hi = pat >> 32;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PAT, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PAT, msr);</span><br><span> }</span><br><span> </span><br><span> /* PAT encoding used in util/x86/x86_page_tables.go. It matches the linux</span><br><span>diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S</span><br><span>index ba5ae3e..a7e4522 100644</span><br><span>--- a/src/cpu/x86/sipi_vector.S</span><br><span>+++ b/src/cpu/x86/sipi_vector.S</span><br><span>@@ -16,6 +16,7 @@</span><br><span> </span><br><span> #include <cpu/x86/cr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> </span><br><span> /* The SIPI vector is responsible for initializing the APs in the system. It</span><br><span> * loads microcode, sets up MSRs, and enables caching before calling into</span><br><span>@@ -25,9 +26,6 @@</span><br><span> #define CODE_SEG 0x10</span><br><span> #define DATA_SEG 0x18</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_UPDT_TRIG 0x79</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_BIOS_SIGN_ID 0x8b</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> .section ".module_parameters", "aw", @progbits</span><br><span> ap_start_params:</span><br><span> gdtaddr:</span><br><span>@@ -145,7 +143,7 @@</span><br><span> </span><br><span> load_microcode:</span><br><span> /* Load new microcode. */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $IA32_UPDT_TRIG, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_BIOS_UPDT_TRIG, %ecx</span><br><span> xor %edx, %edx</span><br><span> mov %edi, %eax</span><br><span> /* The microcode pointer is passed in pointing to the header. Adjust</span><br><span>diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h</span><br><span>index 35059ff..1303148 100644</span><br><span>--- a/src/include/cpu/intel/l2_cache.h</span><br><span>+++ b/src/include/cpu/intel/l2_cache.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #ifndef __P6_L2_CACHE_H</span><br><span> #define __P6_L2_CACHE_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_ID 0x17</span><br><span> #define EBL_CR_POWERON 0x2A</span><br><span> </span><br><span> #define BBL_CR_D0 0x88</span><br><span>diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h</span><br><span>index 4b556b7..03ba89d 100644</span><br><span>--- a/src/include/cpu/intel/speedstep.h</span><br><span>+++ b/src/include/cpu/intel/speedstep.h</span><br><span>@@ -35,11 +35,7 @@</span><br><span> </span><br><span> </span><br><span> /* Speedstep related MSRs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_ID 0x017</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_STATUS 0x198</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_THERM2_CTL 0x19D</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLES 0x1A0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_THERM2_CTL 0x19D</span><br><span> #define MSR_EBC_FREQUENCY_ID 0x2c</span><br><span> #define MSR_FSB_FREQ 0xcd</span><br><span> #define MSR_FSB_CLOCK_VCC 0xce</span><br><span>diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h</span><br><span>index 58f4831..0880ebb 100644</span><br><span>--- a/src/include/cpu/intel/turbo.h</span><br><span>+++ b/src/include/cpu/intel/turbo.h</span><br><span>@@ -20,7 +20,6 @@</span><br><span> #define CPUID_LEAF_PM 6</span><br><span> #define PM_CAP_TURBO_MODE (1 << 1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> /* Disable the Monitor Mwait FSM feature */</span><br><span> #define MONITOR_MWAIT_DIS_MASK 0x40000</span><br><span> </span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 290c54a..489182f 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -13,14 +13,42 @@</span><br><span> #define EFER_SCE (1 << 0)</span><br><span> </span><br><span> /* Page attribute type MSR */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PAT 0x277</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MPERF 0xe7</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_APERF 0xe8</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PM_ENABLE 0x770</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_HWP_CAPABILITIES 0x771</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_HWP_REQUEST 0x774</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_HWP_STATUS 0x777</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PLATFORM_ID 0x17</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define FEATURE_CONTROL_LOCK_BIT (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FEATURE_ENABLE_VMX (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMRR_ENABLE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPUID_SMX (1 << 6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_BIOS_UPDT_TRIG 0x79</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_BIOS_SIGN_ID 0x8b</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MPERF 0xe7</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_APERF 0xe8</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP 0x179</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PERF_STATUS 0x198</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MISC_ENABLE 0x1a0</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_ENERGY_PERF_BIAS 0x1b0</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PAT 0x277</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MC0_STATUS 0x401</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PM_ENABLE 0x770</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_HWP_CAPABILITIES 0x771</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_HWP_REQUEST 0x774</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_HWP_STATUS 0x777</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PQR_ASSOC 0xc8f</span><br><span style="color: hsl(120, 100%, 40%);">+/* MSR bits 33:32 encode slot number 0-3 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ASSEMBLER__</span><br><span> #if defined(__ROMCC__)</span><br><span> </span><br><span> typedef __builtin_msr_t msr_t;</span><br><span>@@ -95,5 +123,5 @@</span><br><span> </span><br><span> #endif /* CONFIG_SOC_SETS_MSRS */</span><br><span> #endif /* __ROMCC__ */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> #endif /* CPU_X86_MSR_H */</span><br><span>diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c</span><br><span>index 0a9b408..1ebb2a5 100644</span><br><span>--- a/src/northbridge/intel/nehalem/early_init.c</span><br><span>+++ b/src/northbridge/intel/nehalem/early_init.c</span><br><span>@@ -110,11 +110,11 @@</span><br><span> m.lo = (m.lo & ~0xff) | reg8;</span><br><span> wrmsr(IA32_PERF_CTL, m);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- m = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ m = rdmsr(IA32_MISC_ENABLE);</span><br><span> m.hi &= ~0x00000040;</span><br><span> m.lo |= 0x10000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, m);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, m);</span><br><span> }</span><br><span> </span><br><span> m = rdmsr(MSR_FSB_CLOCK_VCC);</span><br><span>@@ -124,9 +124,9 @@</span><br><span> m.lo = (m.lo & ~0xff) | reg8;</span><br><span> wrmsr(IA32_PERF_CTL, m);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- m = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ m = rdmsr(IA32_MISC_ENABLE);</span><br><span> m.lo |= 0x10000;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, m);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, m);</span><br><span> }</span><br><span> </span><br><span> void nehalem_early_initialization(int chipset_type)</span><br><span>diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c</span><br><span>index caa3bbf..928679f 100644</span><br><span>--- a/src/soc/intel/apollolake/cpu.c</span><br><span>+++ b/src/soc/intel/apollolake/cpu.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,</span><br><span> (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),</span><br><span> /* Disable support for MONITOR and MWAIT instructions */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0),</span><br><span> #endif</span><br><span> /* Disable C1E */</span><br><span> REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>index 689d4d5..dd60345 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>@@ -16,7 +16,6 @@</span><br><span> #ifndef _BAYTRAIL_MSR_H_</span><br><span> #define _BAYTRAIL_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -24,8 +23,6 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span> #define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span>diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c</span><br><span>index 486f5a3..e9925a2 100644</span><br><span>--- a/src/soc/intel/baytrail/ramstage.c</span><br><span>+++ b/src/soc/intel/baytrail/ramstage.c</span><br><span>@@ -108,7 +108,7 @@</span><br><span> stepping_str[attrs->stepping]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> </span><br><span> /* Set IA core speed ratio and voltages */</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>index dcb6296..9969d5d 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> </span><br><span> #include "fmap_config.h"</span><br><span> </span><br><span>@@ -35,7 +36,6 @@</span><br><span> </span><br><span> #define NoEvictMod_MSR 0x2e0</span><br><span> #define BBL_CR_CTL3_MSR 0x11e</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCG_CAP_MSR 0x179</span><br><span> </span><br><span> /* Save the BIST result. */</span><br><span> movl %eax, %ebp</span><br><span>@@ -64,7 +64,7 @@</span><br><span> </span><br><span> post_code(0x22)</span><br><span> /* Zero the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MCG_CAP_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_MCG_CAP, %ecx</span><br><span> rdmsr</span><br><span> movzx %al, %ebx</span><br><span> /* First variable MTRR. */</span><br><span>diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c</span><br><span>index 66fde22..f9c3014 100644</span><br><span>--- a/src/soc/intel/baytrail/tsc_freq.c</span><br><span>+++ b/src/soc/intel/baytrail/tsc_freq.c</span><br><span>@@ -60,9 +60,9 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of</span><br><span> * the PERF_CTL. */</span><br><span>@@ -74,7 +74,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* __SMM__ */</span><br><span>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c</span><br><span>index 85b04ac..5383fdf 100644</span><br><span>--- a/src/soc/intel/braswell/cpu.c</span><br><span>+++ b/src/soc/intel/braswell/cpu.c</span><br><span>@@ -175,7 +175,7 @@</span><br><span> msr_t msr_value;</span><br><span> </span><br><span> /* Need to make sure that all cores have microcode loaded. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_value = rdmsr(IA32_BIOS_SIGN_ID);</span><br><span> if (msr_value.hi == 0)</span><br><span> intel_microcode_load_unlocked(pattrs->microcode_patch);</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>index 47e9bcd..ec0cbe3 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>@@ -17,8 +17,6 @@</span><br><span> #ifndef _SOC_MSR_H_</span><br><span> #define _SOC_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_BIOS_SIGN_ID 0x8B</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -26,8 +24,6 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span> #define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span>diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c</span><br><span>index 20c09d5..a12db80 100644</span><br><span>--- a/src/soc/intel/braswell/ramstage.c</span><br><span>+++ b/src/soc/intel/braswell/ramstage.c</span><br><span>@@ -112,7 +112,7 @@</span><br><span> stepping_str[attrs->stepping]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> </span><br><span> /* Set IA core speed ratio and voltages */</span><br><span>diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c</span><br><span>index b05a007..72dbca5 100644</span><br><span>--- a/src/soc/intel/braswell/tsc_freq.c</span><br><span>+++ b/src/soc/intel/braswell/tsc_freq.c</span><br><span>@@ -67,14 +67,14 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Enable Burst Mode */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /*</span><br><span> * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of</span><br><span>@@ -91,7 +91,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* ENV_SMM */</span><br><span>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c</span><br><span>index ee1fd52..4c1b3fd 100644</span><br><span>--- a/src/soc/intel/broadwell/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/cpu.c</span><br><span>@@ -546,10 +546,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 41ce17c..c93d292 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -18,9 +18,6 @@</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -32,26 +29,16 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRRphysBase_MSR 0x1f4</span><br><span> #define EMRRphysMask_MSR 0x1f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_EMRRphysBase_MSR 0x2f4</span><br><span> #define UNCORE_EMRRphysMask_MSR 0x2f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c</span><br><span>index ba87045..1fdaf69 100644</span><br><span>--- a/src/soc/intel/cannonlake/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/cpu.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <chip.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <cpu/x86/mp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span> #include <intelblocks/cpulib.h></span><br><span> #include <intelblocks/mp_init.h></span><br><span>@@ -126,10 +127,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> }</span><br><span> </span><br><span> static void configure_c_states(void)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>index 6617d7f..e3bd5f6 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>@@ -20,13 +20,6 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f9</span><br><span> #define MSR_VR_MISC_CONFIG2 0x636</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>index 684f827..17b8dc0 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <commonlib/helpers.h></span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span> #include <rules.h></span><br><span>@@ -306,7 +307,7 @@</span><br><span> wrmsr</span><br><span> </span><br><span> /* Set CLOS selector to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */</span><br><span> wrmsr</span><br><span>@@ -339,7 +340,7 @@</span><br><span> post_code(0x27)</span><br><span> </span><br><span> /* Cache is populated. Use mask 1 that will block evicts */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */</span><br><span> or $1, %edx /* select mask 1 */</span><br><span>@@ -410,7 +411,7 @@</span><br><span> */</span><br><span> shl %cl, %eax</span><br><span> subl $0x02, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MSR_IA32_L3_MASK_1, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_L3_MASK_1, %ecx</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span> /*</span><br><span>@@ -419,12 +420,12 @@</span><br><span> * For SKL SOC, data size remains 256K consistently.</span><br><span> * Hence, creating 1-way associative cache for Data</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_L3_MASK_2, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_L3_MASK_2, %ecx</span><br><span> mov $0x01, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set MSR_IA32_PQR_ASSOC = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set IA32_PQR_ASSOC = 0x02</span><br><span> *</span><br><span> * Possible values:</span><br><span> * 0: Default value, no way mask should be applied</span><br><span>@@ -432,7 +433,7 @@</span><br><span> * 2: Apply way mask 2 to LLC</span><br><span> * 3: Shouldn't be use in NEM Mode</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_PQR_ASSOC, %ecx</span><br><span> movl $0x02, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span>@@ -444,11 +445,11 @@</span><br><span> cld</span><br><span> rep stosl</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set MSR_IA32_PQR_ASSOC = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set IA32_PQR_ASSOC = 0x01</span><br><span> * At this stage we apply LLC_WAY_MASK_1 to the cache.</span><br><span> * i.e. way 0 is protected from eviction.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_PQR_ASSOC, %ecx</span><br><span> movl $0x01, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span>diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S</span><br><span>index 86feddc..a4d16e8 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/car/exit_car.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/exit_car.S</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/cr.h></span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span>@@ -80,7 +81,7 @@</span><br><span> wrmsr</span><br><span> </span><br><span> /* Reset CLOS selector to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx</span><br><span> wrmsr</span><br><span>@@ -101,7 +102,7 @@</span><br><span> wrmsr</span><br><span> </span><br><span> /* Reset CLOS selector to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx</span><br><span> wrmsr</span><br><span>diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>index 112a049..ebbdabd 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>@@ -95,7 +95,7 @@</span><br><span> perf_ctl.lo = (msr.lo & 0xff) << 8;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>@@ -115,7 +115,7 @@</span><br><span> perf_ctl.lo = (msr.lo & 0xff) << 8;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>@@ -135,7 +135,7 @@</span><br><span> perf_ctl.lo = msr.lo & 0xff00;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index e1fc431..b7fe904 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -17,13 +17,6 @@</span><br><span> #define SOC_INTEL_COMMON_MSR_H</span><br><span> </span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_CONTROL_LOCK (1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_ENABLE_VMX (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */</span><br><span>@@ -46,16 +39,13 @@</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL</span><br><span> #define FEATURE_CONFIG_LOCK (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span> #define SMM_MCA_CAP_MSR 0x17d</span><br><span> #define SMM_CPU_SVRSTR_BIT 57</span><br><span> #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */</span><br><span style="color: hsl(120, 100%, 40%);">+/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */</span><br><span> #define BURST_MODE_DISABLE (1 << 6)</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_PREFETCH_CTL 0x1a4</span><br><span>@@ -76,8 +66,6 @@</span><br><span> #define MSR_EVICT_CTL 0x2e0</span><br><span> #define MSR_SGX_OWNEREPOCH0 0x300</span><br><span> #define MSR_SGX_OWNEREPOCH1 0x301</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span>@@ -122,11 +110,8 @@</span><br><span> #define SMBASE_MSR 0xc20</span><br><span> #define IEDBASE_MSR 0xc22</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PQR_ASSOC 0x0c8f</span><br><span style="color: hsl(0, 100%, 40%);">-/* MSR bits 33:32 encode slot number 0-3 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_L3_MASK_1 0x0c91</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_L3_MASK_2 0x0c92</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_L3_MASK_1 0x0c91</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_L3_MASK_2 0x0c92</span><br><span> #define MSR_L2_QOS_MASK(reg) (0xd10 + reg)</span><br><span> </span><br><span> /* MTRR_CAP_MSR bits */</span><br><span>diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>index daedcfc..6050dec 100644</span><br><span>--- a/src/soc/intel/common/block/sgx/sgx.c</span><br><span>+++ b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>@@ -137,7 +137,7 @@</span><br><span> </span><br><span> msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span> /* Only enable it when it is not locked */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) {</span><br><span> msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */</span><br><span> wrmsr(IA32_FEATURE_CONTROL, msr);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c</span><br><span>index 591ffbc..2cffdab 100644</span><br><span>--- a/src/soc/intel/common/block/vmx/vmx.c</span><br><span>+++ b/src/soc/intel/common/block/vmx/vmx.c</span><br><span>@@ -58,7 +58,7 @@</span><br><span> msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span> </span><br><span> /* Only enable it when it is not locked */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) {</span><br><span> /* Enable VMX */</span><br><span> msr.lo |= FEATURE_ENABLE_VMX;</span><br><span> wrmsr(IA32_FEATURE_CONTROL, msr);</span><br><span>@@ -68,5 +68,5 @@</span><br><span> msr = rdmsr(IA32_FEATURE_CONTROL);</span><br><span> printk(BIOS_DEBUG, "VMX status: %s, %s\n",</span><br><span> (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled",</span><br><span style="color: hsl(0, 100%, 40%);">- (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked");</span><br><span style="color: hsl(120, 100%, 40%);">+ (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked");</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c</span><br><span>index b7b5550..676fab7 100644</span><br><span>--- a/src/soc/intel/denverton_ns/cpu.c</span><br><span>+++ b/src/soc/intel/denverton_ns/cpu.c</span><br><span>@@ -44,9 +44,9 @@</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span> if (get_turbo_state() == TURBO_ENABLED) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= SPEED_STEP_ENABLE_BIT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 4d1ac70..082117c 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -18,12 +18,8 @@</span><br><span> #ifndef _DENVERTON_NS_MSR_H_</span><br><span> #define _DENVERTON_NS_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PLATFORM_ID 0x17</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -35,26 +31,16 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRR_PHYS_BASE_MSR 0x1f4</span><br><span> #define EMRR_PHYS_MASK_MSR 0x1f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4</span><br><span> #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>index ea1d790..6a2ce1a 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>@@ -16,13 +16,10 @@</span><br><span> #ifndef _BAYTRAIL_MSR_H_</span><br><span> #define _BAYTRAIL_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>index fc50e64..f4cdaa8 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>@@ -107,7 +107,7 @@</span><br><span> stepping_str[attrs->stepping]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> </span><br><span> /* Set IA core speed ratio and voltages */</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c</span><br><span>index 1e32262..4c91b0a 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span> "Bay Trail-D (Desktop)",</span><br><span> "Bay Trail-M (Mobile)",</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t platform_id = rdmsr(IA32_PLATFORM_ID);</span><br><span> uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK;</span><br><span> </span><br><span> printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ?</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>index 66fde22..f9c3014 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>@@ -60,9 +60,9 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of</span><br><span> * the PERF_CTL. */</span><br><span>@@ -74,7 +74,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* __SMM__ */</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index ffa33da..ed42fdf 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -18,14 +18,9 @@</span><br><span> #ifndef _SOC_MSR_H_</span><br><span> #define _SOC_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span> #define MSR_CONFIG_TDP_NOMINAL 0x648</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c</span><br><span>index 7165080..7b94268 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/ramstage.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/ramstage.c</span><br><span>@@ -76,7 +76,7 @@</span><br><span> printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 417c4bc..605dc00 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -353,10 +353,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index 780f94f..6da9325 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -24,13 +24,6 @@</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28752">change 28752</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28752"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d </div>
<div style="display:none"> Gerrit-Change-Number: 28752 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>