<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28746">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel: Use "cpu/x86/msr.h" for common IA-32 MSRs<br><br>Also correct IA-32 MSRs names.<br><br>Change-Id: Id9ef2dadca74f9f49d6711bd74235ed53c8a6500<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/baytrail/include/soc/msr.h<br>M src/soc/intel/baytrail/ramstage.c<br>M src/soc/intel/baytrail/romstage/cache_as_ram.inc<br>M src/soc/intel/baytrail/tsc_freq.c<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/braswell/include/soc/msr.h<br>M src/soc/intel/braswell/ramstage.c<br>M src/soc/intel/braswell/tsc_freq.c<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/cannonlake/cpu.c<br>M src/soc/intel/cannonlake/include/soc/msr.h<br>M src/soc/intel/common/block/cpu/car/cache_as_ram.S<br>M src/soc/intel/common/block/cpu/car/exit_car.S<br>M src/soc/intel/common/block/cpu/cpulib.c<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/ramstage.c<br>M src/soc/intel/fsp_baytrail/romstage/report_platform.c<br>M src/soc/intel/fsp_baytrail/tsc_freq.c<br>M src/soc/intel/fsp_broadwell_de/cpu.c<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>M src/soc/intel/fsp_broadwell_de/ramstage.c<br>M src/soc/intel/skylake/cpu.c<br>M src/soc/intel/skylake/include/soc/msr.h<br>28 files changed, 56 insertions(+), 120 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/28746/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c</span><br><span>index caa3bbf..928679f 100644</span><br><span>--- a/src/soc/intel/apollolake/cpu.c</span><br><span>+++ b/src/soc/intel/apollolake/cpu.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,</span><br><span> (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),</span><br><span> /* Disable support for MONITOR and MWAIT instructions */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0),</span><br><span> #endif</span><br><span> /* Disable C1E */</span><br><span> REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>index 689d4d5..dd60345 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>@@ -16,7 +16,6 @@</span><br><span> #ifndef _BAYTRAIL_MSR_H_</span><br><span> #define _BAYTRAIL_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -24,8 +23,6 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span> #define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span>diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c</span><br><span>index 486f5a3..e9925a2 100644</span><br><span>--- a/src/soc/intel/baytrail/ramstage.c</span><br><span>+++ b/src/soc/intel/baytrail/ramstage.c</span><br><span>@@ -108,7 +108,7 @@</span><br><span> stepping_str[attrs->stepping]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> </span><br><span> /* Set IA core speed ratio and voltages */</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>index dcb6296..9969d5d 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> </span><br><span> #include "fmap_config.h"</span><br><span> </span><br><span>@@ -35,7 +36,6 @@</span><br><span> </span><br><span> #define NoEvictMod_MSR 0x2e0</span><br><span> #define BBL_CR_CTL3_MSR 0x11e</span><br><span style="color: hsl(0, 100%, 40%);">-#define MCG_CAP_MSR 0x179</span><br><span> </span><br><span> /* Save the BIST result. */</span><br><span> movl %eax, %ebp</span><br><span>@@ -64,7 +64,7 @@</span><br><span> </span><br><span> post_code(0x22)</span><br><span> /* Zero the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MCG_CAP_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_MCG_CAP, %ecx</span><br><span> rdmsr</span><br><span> movzx %al, %ebx</span><br><span> /* First variable MTRR. */</span><br><span>diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c</span><br><span>index 66fde22..f9c3014 100644</span><br><span>--- a/src/soc/intel/baytrail/tsc_freq.c</span><br><span>+++ b/src/soc/intel/baytrail/tsc_freq.c</span><br><span>@@ -60,9 +60,9 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of</span><br><span> * the PERF_CTL. */</span><br><span>@@ -74,7 +74,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* __SMM__ */</span><br><span>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c</span><br><span>index 85b04ac..5383fdf 100644</span><br><span>--- a/src/soc/intel/braswell/cpu.c</span><br><span>+++ b/src/soc/intel/braswell/cpu.c</span><br><span>@@ -175,7 +175,7 @@</span><br><span> msr_t msr_value;</span><br><span> </span><br><span> /* Need to make sure that all cores have microcode loaded. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_value = rdmsr(IA32_BIOS_SIGN_ID);</span><br><span> if (msr_value.hi == 0)</span><br><span> intel_microcode_load_unlocked(pattrs->microcode_patch);</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>index 47e9bcd..ec0cbe3 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>@@ -17,8 +17,6 @@</span><br><span> #ifndef _SOC_MSR_H_</span><br><span> #define _SOC_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_BIOS_SIGN_ID 0x8B</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -26,8 +24,6 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span> #define ENABLE_INDP_AUTOCM_MASK (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span>diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c</span><br><span>index 20c09d5..a12db80 100644</span><br><span>--- a/src/soc/intel/braswell/ramstage.c</span><br><span>+++ b/src/soc/intel/braswell/ramstage.c</span><br><span>@@ -112,7 +112,7 @@</span><br><span> stepping_str[attrs->stepping]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> </span><br><span> /* Set IA core speed ratio and voltages */</span><br><span>diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c</span><br><span>index b05a007..72dbca5 100644</span><br><span>--- a/src/soc/intel/braswell/tsc_freq.c</span><br><span>+++ b/src/soc/intel/braswell/tsc_freq.c</span><br><span>@@ -67,14 +67,14 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Enable Burst Mode */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /*</span><br><span> * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of</span><br><span>@@ -91,7 +91,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* ENV_SMM */</span><br><span>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c</span><br><span>index ee1fd52..4c1b3fd 100644</span><br><span>--- a/src/soc/intel/broadwell/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/cpu.c</span><br><span>@@ -546,10 +546,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 41ce17c..c93d292 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -18,9 +18,6 @@</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -32,26 +29,16 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRRphysBase_MSR 0x1f4</span><br><span> #define EMRRphysMask_MSR 0x1f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_EMRRphysBase_MSR 0x2f4</span><br><span> #define UNCORE_EMRRphysMask_MSR 0x2f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c</span><br><span>index ba87045..1fdaf69 100644</span><br><span>--- a/src/soc/intel/cannonlake/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/cpu.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <chip.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <cpu/x86/mp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/intel/turbo.h></span><br><span> #include <intelblocks/cpulib.h></span><br><span> #include <intelblocks/mp_init.h></span><br><span>@@ -126,10 +127,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> }</span><br><span> </span><br><span> static void configure_c_states(void)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>index 6617d7f..e3bd5f6 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/msr.h</span><br><span>@@ -20,13 +20,6 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f9</span><br><span> #define MSR_VR_MISC_CONFIG2 0x636</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>index 684f827..17b8dc0 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <commonlib/helpers.h></span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span> #include <rules.h></span><br><span>@@ -306,7 +307,7 @@</span><br><span> wrmsr</span><br><span> </span><br><span> /* Set CLOS selector to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */</span><br><span> wrmsr</span><br><span>@@ -339,7 +340,7 @@</span><br><span> post_code(0x27)</span><br><span> </span><br><span> /* Cache is populated. Use mask 1 that will block evicts */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */</span><br><span> or $1, %edx /* select mask 1 */</span><br><span>@@ -410,7 +411,7 @@</span><br><span> */</span><br><span> shl %cl, %eax</span><br><span> subl $0x02, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MSR_IA32_L3_MASK_1, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_L3_MASK_1, %ecx</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span> /*</span><br><span>@@ -419,12 +420,12 @@</span><br><span> * For SKL SOC, data size remains 256K consistently.</span><br><span> * Hence, creating 1-way associative cache for Data</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_L3_MASK_2, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_L3_MASK_2, %ecx</span><br><span> mov $0x01, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set MSR_IA32_PQR_ASSOC = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set IA32_PQR_ASSOC = 0x02</span><br><span> *</span><br><span> * Possible values:</span><br><span> * 0: Default value, no way mask should be applied</span><br><span>@@ -432,7 +433,7 @@</span><br><span> * 2: Apply way mask 2 to LLC</span><br><span> * 3: Shouldn't be use in NEM Mode</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_PQR_ASSOC, %ecx</span><br><span> movl $0x02, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span>@@ -444,11 +445,11 @@</span><br><span> cld</span><br><span> rep stosl</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set MSR_IA32_PQR_ASSOC = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set IA32_PQR_ASSOC = 0x01</span><br><span> * At this stage we apply LLC_WAY_MASK_1 to the cache.</span><br><span> * i.e. way 0 is protected from eviction.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $IA32_PQR_ASSOC, %ecx</span><br><span> movl $0x01, %eax</span><br><span> xorl %edx, %edx</span><br><span> wrmsr</span><br><span>diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S</span><br><span>index 86feddc..a4d16e8 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/car/exit_car.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/exit_car.S</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span> #include <cpu/x86/cr.h></span><br><span> #include <intelblocks/msr.h></span><br><span> </span><br><span>@@ -80,7 +81,7 @@</span><br><span> wrmsr</span><br><span> </span><br><span> /* Reset CLOS selector to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx</span><br><span> wrmsr</span><br><span>@@ -101,7 +102,7 @@</span><br><span> wrmsr</span><br><span> </span><br><span> /* Reset CLOS selector to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $MSR_IA32_PQR_ASSOC, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IA32_PQR_ASSOC, %ecx</span><br><span> rdmsr</span><br><span> and $~IA32_PQR_ASSOC_MASK, %edx</span><br><span> wrmsr</span><br><span>diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>index 112a049..ebbdabd 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>@@ -95,7 +95,7 @@</span><br><span> perf_ctl.lo = (msr.lo & 0xff) << 8;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>@@ -115,7 +115,7 @@</span><br><span> perf_ctl.lo = (msr.lo & 0xff) << 8;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>@@ -135,7 +135,7 @@</span><br><span> perf_ctl.lo = msr.lo & 0xff00;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",</span><br><span> ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index e1fc431..b7fe904 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -17,13 +17,6 @@</span><br><span> #define SOC_INTEL_COMMON_MSR_H</span><br><span> </span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_CONTROL_LOCK (1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FEATURE_ENABLE_VMX (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */</span><br><span>@@ -46,16 +39,13 @@</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL</span><br><span> #define FEATURE_CONFIG_LOCK (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MCG_CAP 0x179</span><br><span> #define SMM_MCA_CAP_MSR 0x17d</span><br><span> #define SMM_CPU_SVRSTR_BIT 57</span><br><span> #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span style="color: hsl(0, 100%, 40%);">-/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */</span><br><span style="color: hsl(120, 100%, 40%);">+/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */</span><br><span> #define BURST_MODE_DISABLE (1 << 6)</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_PREFETCH_CTL 0x1a4</span><br><span>@@ -76,8 +66,6 @@</span><br><span> #define MSR_EVICT_CTL 0x2e0</span><br><span> #define MSR_SGX_OWNEREPOCH0 0x300</span><br><span> #define MSR_SGX_OWNEREPOCH1 0x301</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span>@@ -122,11 +110,8 @@</span><br><span> #define SMBASE_MSR 0xc20</span><br><span> #define IEDBASE_MSR 0xc22</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PQR_ASSOC 0x0c8f</span><br><span style="color: hsl(0, 100%, 40%);">-/* MSR bits 33:32 encode slot number 0-3 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_L3_MASK_1 0x0c91</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_L3_MASK_2 0x0c92</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_L3_MASK_1 0x0c91</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_L3_MASK_2 0x0c92</span><br><span> #define MSR_L2_QOS_MASK(reg) (0xd10 + reg)</span><br><span> </span><br><span> /* MTRR_CAP_MSR bits */</span><br><span>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c</span><br><span>index b7b5550..676fab7 100644</span><br><span>--- a/src/soc/intel/denverton_ns/cpu.c</span><br><span>+++ b/src/soc/intel/denverton_ns/cpu.c</span><br><span>@@ -44,9 +44,9 @@</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span> if (get_turbo_state() == TURBO_ENABLED) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= SPEED_STEP_ENABLE_BIT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 4d1ac70..082117c 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -18,12 +18,8 @@</span><br><span> #ifndef _DENVERTON_NS_MSR_H_</span><br><span> #define _DENVERTON_NS_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PLATFORM_ID 0x17</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_FEATURE_CONTROL 0x3a</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_VMX (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -35,26 +31,16 @@</span><br><span> #define MSR_FLEX_RATIO 0x194</span><br><span> #define FLEX_RATIO_LOCK (1 << 20)</span><br><span> #define FLEX_RATIO_EN (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MISC_ENABLE 0x1a0</span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span> #define EMRR_PHYS_BASE_MSR 0x1f4</span><br><span> #define EMRR_PHYS_MASK_MSR 0x1f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4</span><br><span> #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>index ea1d790..6a2ce1a 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>@@ -16,13 +16,10 @@</span><br><span> #ifndef _BAYTRAIL_MSR_H_</span><br><span> #define _BAYTRAIL_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PERF_CTL 0x199</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>index fc50e64..f4cdaa8 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/ramstage.c</span><br><span>@@ -107,7 +107,7 @@</span><br><span> stepping_str[attrs->stepping]);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> </span><br><span> /* Set IA core speed ratio and voltages */</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c</span><br><span>index 1e32262..4c91b0a 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span> "Bay Trail-D (Desktop)",</span><br><span> "Bay Trail-M (Mobile)",</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t platform_id = rdmsr(IA32_PLATFORM_ID);</span><br><span> uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK;</span><br><span> </span><br><span> printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ?</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>index 66fde22..f9c3014 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c</span><br><span>@@ -60,9 +60,9 @@</span><br><span> msr_t msr;</span><br><span> </span><br><span> /* Enable speed step. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= (1 << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MISC_ENABLES, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span> /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of</span><br><span> * the PERF_CTL. */</span><br><span>@@ -74,7 +74,7 @@</span><br><span> perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;</span><br><span> perf_ctl.hi = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_PERF_CTL, perf_ctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_PERF_CTL, perf_ctl);</span><br><span> }</span><br><span> </span><br><span> #endif /* __SMM__ */</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c</span><br><span>index a50c839..a10e504 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/cpu.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/cpu.c</span><br><span>@@ -128,11 +128,10 @@</span><br><span> static void configure_mca(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned int mcg_cap_msr = 0x179;</span><br><span> int i;</span><br><span> int num_banks;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(mcg_cap_msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MCG_CAP);</span><br><span> num_banks = msr.lo & 0xff;</span><br><span> </span><br><span> /* TODO(adurbin): This should only be done on a cold boot. Also, some</span><br><span>@@ -140,14 +139,17 @@</span><br><span> every bank. */</span><br><span> msr.lo = msr.hi = 0;</span><br><span> for (i = 0; i < num_banks; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear the machine check status */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr);</span><br><span> }</span><br><span> </span><br><span> msr.lo = msr.hi = 0xffffffff;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < num_banks; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize machine checks */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_CTL + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> static void broadwell_de_core_init(struct device *cpu)</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index 6b87061..ed42fdf 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -18,12 +18,9 @@</span><br><span> #ifndef _SOC_MSR_H_</span><br><span> #define _SOC_MSR_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PERF_CTL 0x199</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MC0_STATUS 0x400</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span> #define MSR_CONFIG_TDP_NOMINAL 0x648</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c</span><br><span>index 7165080..7b94268 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/ramstage.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/ramstage.c</span><br><span>@@ -76,7 +76,7 @@</span><br><span> printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);</span><br><span> fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 417c4bc..605dc00 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -353,10 +353,10 @@</span><br><span> return;</span><br><span> </span><br><span> /* Energy Policy is bits 3:0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);</span><br><span> msr.lo &= ~0xf;</span><br><span> msr.lo |= policy & 0xf;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>index 780f94f..6da9325 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/msr.h</span><br><span>@@ -24,13 +24,6 @@</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_THERM_INTERRUPT 0x19b</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_PERFORMANCE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_NORMAL 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4</span><br><span> #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28746">change 28746</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id9ef2dadca74f9f49d6711bd74235ed53c8a6500 </div>
<div style="display:none"> Gerrit-Change-Number: 28746 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>