<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28751">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names<br><br>Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and<br>IA32_MC0_CTL is at 0x400.<br>So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at<br>0x400 by IA32_MC0_CTL.<br><br>Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/fsp_broadwell_de/cpu.c<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>2 files changed, 12 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28751/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c</span><br><span>index a50c839..a10e504 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/cpu.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/cpu.c</span><br><span>@@ -128,11 +128,10 @@</span><br><span> static void configure_mca(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- const unsigned int mcg_cap_msr = 0x179;</span><br><span> int i;</span><br><span> int num_banks;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(mcg_cap_msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MCG_CAP);</span><br><span> num_banks = msr.lo & 0xff;</span><br><span> </span><br><span> /* TODO(adurbin): This should only be done on a cold boot. Also, some</span><br><span>@@ -140,14 +139,17 @@</span><br><span> every bank. */</span><br><span> msr.lo = msr.hi = 0;</span><br><span> for (i = 0; i < num_banks; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear the machine check status */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr);</span><br><span> }</span><br><span> </span><br><span> msr.lo = msr.hi = 0xffffffff;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < num_banks; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_IA32_MC0_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize machine checks */</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MC0_CTL + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> static void broadwell_de_core_init(struct device *cpu)</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index 6b87061..ffa33da 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -21,9 +21,11 @@</span><br><span> #define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP 0x179</span><br><span> #define IA32_PERF_CTL 0x199</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MC0_STATUS 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MC0_STATUS 0x401</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span> #define MSR_CONFIG_TDP_NOMINAL 0x648</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28751">change 28751</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28751"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 </div>
<div style="display:none"> Gerrit-Change-Number: 28751 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>