<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28730">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl1: Make the DDR memory swizzle data configurable<br><br>In preparation for a future MC Apollo Lake board which will be equipped<br>with LPDDR4 modules, it is necessary to make the swizzle data<br>configurable. Starting from the mc_apl1 baseboard, which is equipped<br>with DDR3L memory and therefore does not need swizzle data, the<br>structures are initialized with zero.<br><br>Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/romstage.c<br>M src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc<br>M src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c<br>4 files changed, 143 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28730/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c</span><br><span>index d56c7ee..f2786cf 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/romstage.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/romstage.c</span><br><span>@@ -18,39 +18,18 @@</span><br><span> #include <hwilib.h></span><br><span> #include <lib.h></span><br><span> #include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/meminit.h></span><br><span> #include <soc/romstage.h></span><br><span> #include <fsp/api.h></span><br><span> #include <FspmUpd.h></span><br><span> #include <baseboard/variants.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const uint8_t Ch0_Bit_swizzling[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-static const uint8_t Ch1_Bit_swizzling[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-static const uint8_t Ch2_Bit_swizzling[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-static const uint8_t Ch3_Bit_swizzling[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void mainboard_memory_init_params(FSPM_UPD *memupd)</span><br><span> {</span><br><span> const struct pad_config *pads;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct lpddr4_swizzle_cfg *cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct lpddr4_chan_swizzle_cfg *chan;</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t sz = DQ_BITS_PER_DQS;</span><br><span> uint8_t spd[0x80];</span><br><span> size_t num;</span><br><span> </span><br><span>@@ -58,7 +37,8 @@</span><br><span> pads = variant_early_gpio_table(&num);</span><br><span> gpio_configure_pads(pads, num);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Get DRAM configuration data from hwinfo block.</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Get DRAM configuration data from hwinfo block.</span><br><span> * The configuration data from hwinfo block is a one-to-one</span><br><span> * representation of the FSPM_UPD data starting with parameter</span><br><span> * 'Package' (offset 0x4d) and ending before parameter</span><br><span>@@ -80,14 +60,70 @@</span><br><span> (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)-</span><br><span> (&memupd->FspmConfig.Package)));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(Ch0_Bit_swizzling));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(Ch1_Bit_swizzling));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(Ch2_Bit_swizzling));</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(Ch3_Bit_swizzling));</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Some of the mc_apl1 boards use LPDDR4 memory. In this case, the</span><br><span style="color: hsl(120, 100%, 40%);">+ * correct swizzle configuration is necessary. The default settings</span><br><span style="color: hsl(120, 100%, 40%);">+ * for swizzling are 0, since the baseboard does not use LPDDR4 memory.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg = variant_lpddr4_swizzle_config();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * CH0_DQB byte lanes in the bit swizzle configuration field are</span><br><span style="color: hsl(120, 100%, 40%);">+ * not 1:1. The mapping within the swizzling field is:</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ chan = &cfg->phys[LP4_PHYS_CH0B];</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[8], &chan->dqs[LP4_DQS0],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[16], &chan->dqs[LP4_DQS3],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[24], &chan->dqs[LP4_DQS2],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ chan = &cfg->phys[LP4_PHYS_CH0A];</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[0], &chan->dqs[LP4_DQS0],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[8], &chan->dqs[LP4_DQS1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[16], &chan->dqs[LP4_DQS2],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * CH1_DQB byte lanes in the bit swizzle configuration field are</span><br><span style="color: hsl(120, 100%, 40%);">+ * not 1:1. The mapping within the swizzling field is:</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [0:7] - byte lane 1 (DQS1) DQ[8:15]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [8:15] - byte lane 0 (DQS0) DQ[0:7]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [16:23] - byte lane 3 (DQS3) DQ[24:31]</span><br><span style="color: hsl(120, 100%, 40%);">+ * indices [24:31] - byte lane 2 (DQS2) DQ[16:23]</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ chan = &cfg->phys[LP4_PHYS_CH1B];</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[8], &chan->dqs[LP4_DQS0],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[16], &chan->dqs[LP4_DQS3],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[24], &chan->dqs[LP4_DQS2],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CH1_DQA byte lanes in the bit swizzle configuration field are 1:1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ chan = &cfg->phys[LP4_PHYS_CH1A];</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[0], &chan->dqs[LP4_DQS0],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[8], &chan->dqs[LP4_DQS1],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[16], &chan->dqs[LP4_DQS2],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3],</span><br><span style="color: hsl(120, 100%, 40%);">+ sz);</span><br><span> </span><br><span> memupd->FspmConfig.MsgLevelMask = 0x0;</span><br><span> memupd->FspmConfig.MrcDataSaving = 0x0;</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc</span><br><span>index e3e87ce..07ebf9b 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc</span><br><span>@@ -1,3 +1,4 @@</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memory.c</span><br><span> </span><br><span> ramstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h</span><br><span>index 09153c6..6828ed8 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -26,6 +26,9 @@</span><br><span> const struct pad_config *variant_gpio_table(size_t *num);</span><br><span> const struct pad_config *variant_early_gpio_table(size_t *num);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* This function provides the swizzle data for the DRAM initialization. */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* The following function performs board specific things. */</span><br><span> void variant_mainboard_final(void);</span><br><span> </span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c</span><br><span>new file mode 100644</span><br><span>index 0000000..13b7ab8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c</span><br><span>@@ -0,0 +1,69 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2016 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/meminit.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */</span><br><span style="color: hsl(120, 100%, 40%);">+ .phys[LP4_PHYS_CH0A] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[0:7] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[8:15] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .phys[LP4_PHYS_CH0B] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[0:7] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[8:15] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .phys[LP4_PHYS_CH1A] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[0:7] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[8:15] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .phys[LP4_PHYS_CH1B] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[0:7] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQA[8:15] pins of LPDDR4 module. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct lpddr4_swizzle_cfg * __weak variant_lpddr4_swizzle_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return &baseboard_lpddr4_swizzle;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28730">change 28730</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e </div>
<div style="display:none"> Gerrit-Change-Number: 28730 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>