<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28719">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/pi/hudson: Add SPI controller support<br><br>Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>M src/southbridge/amd/pi/hudson/Makefile.inc<br>A src/southbridge/amd/pi/hudson/spi.c<br>2 files changed, 176 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/28719/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc</span><br><span>index 251cb6c..e06973a 100644</span><br><span>--- a/src/southbridge/amd/pi/hudson/Makefile.inc</span><br><span>+++ b/src/southbridge/amd/pi/hudson/Makefile.inc</span><br><span>@@ -55,6 +55,7 @@</span><br><span> ramstage-y += sm.c</span><br><span> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c</span><br><span> ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> ramstage-$(CONFIG_HUDSON_UART) += uart.c</span><br><span> ramstage-y += usb.c</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/pi/hudson/spi.c b/src/southbridge/amd/pi/hudson/spi.c</span><br><span>new file mode 100644</span><br><span>index 0000000..76373c4</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/amd/pi/hudson/spi.c</span><br><span>@@ -0,0 +1,175 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spi_flash.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spi-generic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Proc/Fch/FchPlatform.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_REG_OPCODE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_REG_CNTRL02 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+ #define CNTRL02_FIFO_RESET (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ #define CNTRL02_EXEC_OPCODE (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_REG_CNTRL03 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+ #define CNTRL03_SPIBUSY (1 << 7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_REG_FIFO 0xc</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_REG_CNTRL11 0xd</span><br><span style="color: hsl(120, 100%, 40%);">+ #define CNTRL11_FIFOPTR_MASK 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_EXT_REG_INDX 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SPI_EXT_REG_TXCOUNT 0x5</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SPI_EXT_REG_RXCOUNT 0x6</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_EXT_REG_DATA 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define AMD_SB_SPI_TX_LEN 64</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uintptr_t spibar;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline uint8_t spi_read(uint8_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return read8((void *)(spibar + reg));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void spi_write(uint8_t reg, uint8_t val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((void *)(spibar + reg), val);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void reset_internal_fifo_pointer(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = spi_read(SPI_REG_CNTRL02);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= CNTRL02_FIFO_RESET;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_REG_CNTRL02, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void execute_command(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = spi_read(SPI_REG_CNTRL02);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= CNTRL02_EXEC_OPCODE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_REG_CNTRL02, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void spi_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));</span><br><span style="color: hsl(120, 100%, 40%);">+ spibar = pci_read_config32(dev, 0xA0) & ~0x1F;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t bytesout, void *din, size_t bytesin)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* First byte is cmd which can not being sent through FIFO. */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cmd = *(u8 *)dout++;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t count;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bytesout--;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Check if this is a write command attempting to transfer more bytes</span><br><span style="color: hsl(120, 100%, 40%);">+ * than the controller can handle. Iterations for writes are not</span><br><span style="color: hsl(120, 100%, 40%);">+ * supported here because each SPI write command needs to be preceded</span><br><span style="color: hsl(120, 100%, 40%);">+ * and followed by other SPI commands, and this sequence is controlled</span><br><span style="color: hsl(120, 100%, 40%);">+ * by the SPI chip driver.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bytesout > AMD_SB_SPI_TX_LEN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING, "FCH SPI: Too much to write. Does your SPI chip driver use"</span><br><span style="color: hsl(120, 100%, 40%);">+ " spi_crop_chunk()?\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_EXT_REG_INDX, SPI_EXT_REG_TXCOUNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_EXT_REG_DATA, bytesout);</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_EXT_REG_INDX, SPI_EXT_REG_RXCOUNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_EXT_REG_DATA, bytesin);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_REG_OPCODE, cmd);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_internal_fifo_pointer();</span><br><span style="color: hsl(120, 100%, 40%);">+ for (count = 0; count < bytesout; count++, dout++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_write(SPI_REG_FIFO, *(uint8_t *)dout);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_internal_fifo_pointer();</span><br><span style="color: hsl(120, 100%, 40%);">+ execute_command();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_internal_fifo_pointer();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Skip the bytes we sent. */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (count = 0; count < bytesout; count++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd = spi_read(SPI_REG_FIFO);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (count = 0; count < bytesin; count++, din++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ *(uint8_t *)din = spi_read(SPI_REG_FIFO);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int chipset_volatile_group_begin(const struct spi_flash *flash)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ImcSleep(NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int chipset_volatile_group_end(const struct spi_flash *flash)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ImcWakeup(NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int xfer_vectors(const struct spi_slave *slave,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct spi_op vectors[], size_t count)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct spi_ctrlr spi_ctrlr = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .xfer_vector = xfer_vectors,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_xfer_size = AMD_SB_SPI_TX_LEN,</span><br><span style="color: hsl(120, 100%, 40%);">+ .flags = SPI_CNTRLR_DEDUCT_CMD_LEN,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .ctrlr = &spi_ctrlr,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bus_start = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bus_end = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28719">change 28719</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28719"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd </div>
<div style="display:none"> Gerrit-Change-Number: 28719 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>