<p>dhaval v sharma has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28696">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Make usage of SMI optional where possible<br><br>Make usage of SMI optional where possible 3 different<br>hooks provided as such:<br>1. Most modern OSes are ACPI aware-avoid ACPI switch SMI if<br> possible.<br>2. Avoid finalize soc SMI. Most finalize implementation<br> can be done in normal code.<br>3. Do not need to disable ACPI during boot - leave it<br> enabled through boot.<br><br>Note: With reduced SMI PWRBTN event based graceful shutdown<br>will not work until OS is booted.<br><br>BUG=None<br>BRANCH=None<br>TEST=Booted Soraka with option enabled/disabled.<br><br>Change-Id: I3f0c64b15ed6d0854ff350fcd75d299e45c23f18<br>Signed-off-by: Dhaval <dhaval.v.sharma@intel.com><br>---<br>M src/ec/google/chromeec/ec.c<br>M src/soc/intel/common/block/smm/Kconfig<br>M src/soc/intel/skylake/acpi.c<br>M src/soc/intel/skylake/finalize.c<br>M src/soc/intel/skylake/pmc.c<br>5 files changed, 26 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28696/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c</span><br><span>index 09550d5..f2f4e0d 100644</span><br><span>--- a/src/ec/google/chromeec/ec.c</span><br><span>+++ b/src/ec/google/chromeec/ec.c</span><br><span>@@ -474,9 +474,6 @@</span><br><span> while (google_chromeec_get_event() != 0)</span><br><span> ;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore SCI event mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- google_chromeec_set_sci_mask(info->sci_events);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> } else {</span><br><span> google_chromeec_set_smi_mask(info->smi_events);</span><br><span> </span><br><span>@@ -489,6 +486,13 @@</span><br><span> info->s3_wake_events,</span><br><span> info->s0ix_wake_events);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should be okay to set sci mask for s0 path also because</span><br><span style="color: hsl(120, 100%, 40%);">+ * anyways SCI interrupt gets enabled later during finalize</span><br><span style="color: hsl(120, 100%, 40%);">+ * stage and ACPI_DISABLE calls can explicitely disable it</span><br><span style="color: hsl(120, 100%, 40%);">+ * as required this helps with SMI_REDUCED implementation*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ google_chromeec_set_sci_mask(info->sci_events);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> /* Clear wake event mask. */</span><br><span> google_chromeec_set_wake_mask(0);</span><br><span>diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig</span><br><span>index 909382e..064d4d8 100644</span><br><span>--- a/src/soc/intel/common/block/smm/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/smm/Kconfig</span><br><span>@@ -16,3 +16,9 @@</span><br><span> Time in milliseconds that SLP_SMI for S5 waits for before</span><br><span> enabling sleep. This is required to avoid any race between</span><br><span> SLP_SMI and PWRBTN SMI.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config REDUCED_SMI</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Reduce SMI usage during boot"</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Reduce SMI usage</span><br><span>diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c</span><br><span>index d2ec7e7..5f018ef 100644</span><br><span>--- a/src/soc/intel/skylake/acpi.c</span><br><span>+++ b/src/soc/intel/skylake/acpi.c</span><br><span>@@ -244,7 +244,13 @@</span><br><span> fadt->header.revision = get_acpi_table_revision(FADT);</span><br><span> </span><br><span> fadt->sci_int = acpi_sci_irq();</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->smi_cmd = APM_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_REDUCED_SMI))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI 2.0: if SMI_CMD in FADT is zero no SMI transitions supported */</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->smi_cmd = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->smi_cmd = APM_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> fadt->acpi_enable = APM_CNT_ACPI_ENABLE;</span><br><span> fadt->acpi_disable = APM_CNT_ACPI_DISABLE;</span><br><span> fadt->s4bios_req = 0x0;</span><br><span>diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c</span><br><span>index 4c8a129..996088d 100644</span><br><span>--- a/src/soc/intel/skylake/finalize.c</span><br><span>+++ b/src/soc/intel/skylake/finalize.c</span><br><span>@@ -144,9 +144,10 @@</span><br><span> </span><br><span> soc_lockdown(dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Finalizing SMM.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_REDUCED_SMI)){</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Finalizing SMM.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> /* Indicate finalize step with post code */</span><br><span> post_code(POST_OS_BOOT);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c</span><br><span>index a2623d9..4f77414 100644</span><br><span>--- a/src/soc/intel/skylake/pmc.c</span><br><span>+++ b/src/soc/intel/skylake/pmc.c</span><br><span>@@ -190,7 +190,8 @@</span><br><span> /* Note that certain bits may be cleared from running script as</span><br><span> * certain bit fields are write 1 to clear. */</span><br><span> reg_script_run_on_dev(dev, pch_pmc_misc_init_script);</span><br><span style="color: hsl(0, 100%, 40%);">- pmc_set_acpi_mode();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_REDUCED_SMI))</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_set_acpi_mode();</span><br><span> </span><br><span> config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);</span><br><span> config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28696">change 28696</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3f0c64b15ed6d0854ff350fcd75d299e45c23f18 </div>
<div style="display:none"> Gerrit-Change-Number: 28696 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: dhaval v sharma <dhaval.v.sharma@intel.com> </div>