<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28667">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Init PLLs for DRAM<br><br>Setup DRAM related PLLs.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui<br><br>Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/pll.c<br>1 file changed, 24 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28667/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c</span><br><span>index e0dd388..33a2b0a 100644</span><br><span>--- a/src/soc/mediatek/mt8183/pll.c</span><br><span>+++ b/src/soc/mediatek/mt8183/pll.c</span><br><span>@@ -280,6 +280,28 @@</span><br><span>         setbits_le32(pll->div_reg, PLL_PCW_CHG);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void mem_pll_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+       /* CLKSQ Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+    setbits_le32(&mtk_apmixed->ap_pll_con0, 0x85);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        /* power on MPLL */</span><br><span style="color: hsl(120, 100%, 40%);">+   setbits_le32(&mtk_apmixed->mpll_pwr_con0, 0x3);</span><br><span style="color: hsl(120, 100%, 40%);">+        udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  /* turn off ISO of MPLL */</span><br><span style="color: hsl(120, 100%, 40%);">+    setbits_le32(&mtk_apmixed->mpll_pwr_con0, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+        udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  /* Config MPLL freq */</span><br><span style="color: hsl(120, 100%, 40%);">+        setbits_le32(&mtk_apmixed->mpll_con1, 0x80000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* enable MPLL */</span><br><span style="color: hsl(120, 100%, 40%);">+     setbits_le32(&mtk_apmixed->mpll_con0, 0x181);</span><br><span style="color: hsl(120, 100%, 40%);">+  udelay(20);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void mt_pll_init(void)</span><br><span> {</span><br><span>      int i;</span><br><span>@@ -348,4 +370,6 @@</span><br><span> </span><br><span>     /* enable [14] dramc_pll104m_ck */</span><br><span>   setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+  mem_pll_init();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28667">change 28667</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28667"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab </div>
<div style="display:none"> Gerrit-Change-Number: 28667 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>