<p>Justin TerAvest has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28663">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Create ampton variant<br><br>This creates an ampton variant for Octopus. The initial settings were<br>copied from Bip, but the followint changes were made to support hardware<br>changes:<br> * GPIO_66 is not connected (LTE).<br> * GPIO_67 is not connected (LTE).<br> * Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet.<br> * Pen connection interrupts are on PEN_INT_ODL at GPIO_139.<br> * GPIO_143 is not connected.<br> * GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected.<br> * EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146.<br> * GPIO_213 is not connected.<br> * GPIO_214 is not connected.<br><br>BUG=111498206<br>TEST=None<br><br>Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3<br>Signed-off-by: Justin TerAvest <teravest@chromium.org><br>---<br>M src/mainboard/google/octopus/Kconfig<br>M src/mainboard/google/octopus/Kconfig.name<br>A src/mainboard/google/octopus/variants/ampton/Makefile.inc<br>A src/mainboard/google/octopus/variants/ampton/gpio.c<br>A src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl<br>A src/mainboard/google/octopus/variants/ampton/include/variant/ec.h<br>A src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h<br>A src/mainboard/google/octopus/variants/ampton/overridetree.cb<br>8 files changed, 449 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/28663/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig</span><br><span>index 3ed88bd..e0f3ff1 100644</span><br><span>--- a/src/mainboard/google/octopus/Kconfig</span><br><span>+++ b/src/mainboard/google/octopus/Kconfig</span><br><span>@@ -52,6 +52,7 @@</span><br><span> default "fleex" if BOARD_GOOGLE_FLEEX</span><br><span> default "bobba" if BOARD_GOOGLE_BOBBA</span><br><span> default "meep" if BOARD_GOOGLE_MEEP</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ampton" if BOARD_GOOGLE_AMPTON</span><br><span> default "octopus" if BOARD_GOOGLE_OCTOPUS</span><br><span> </span><br><span> config DEVICETREE</span><br><span>@@ -70,6 +71,7 @@</span><br><span> default "Fleex" if BOARD_GOOGLE_FLEEX</span><br><span> default "Bobba" if BOARD_GOOGLE_BOBBA</span><br><span> default "Meep" if BOARD_GOOGLE_MEEP</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Ampton" if BOARD_GOOGLE_AMPTON</span><br><span> default "Octopus" if BOARD_GOOGLE_OCTOPUS</span><br><span> </span><br><span> config MAINBOARD_FAMILY</span><br><span>@@ -85,6 +87,7 @@</span><br><span> default "FLEEX TEST 7423" if BOARD_GOOGLE_FLEEX</span><br><span> default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA</span><br><span> default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP</span><br><span style="color: hsl(120, 100%, 40%);">+ default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON</span><br><span> default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS</span><br><span> </span><br><span> config MAX_CPUS</span><br><span>@@ -124,6 +127,7 @@</span><br><span> default 9 if BOARD_GOOGLE_FLEEX</span><br><span> default 9 if BOARD_GOOGLE_BOBBA</span><br><span> default 9 if BOARD_GOOGLE_MEEP</span><br><span style="color: hsl(120, 100%, 40%);">+ default 255 if BOARD_GOOGLE_AMPTON</span><br><span> default 255 if BOARD_GOOGLE_OCTOPUS</span><br><span> </span><br><span> endif # BOARD_GOOGLE_OCTOPUS</span><br><span>diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name</span><br><span>index 633a456..a6ee8d0 100644</span><br><span>--- a/src/mainboard/google/octopus/Kconfig.name</span><br><span>+++ b/src/mainboard/google/octopus/Kconfig.name</span><br><span>@@ -40,3 +40,9 @@</span><br><span> select BASEBOARD_OCTOPUS_LAPTOP</span><br><span> select BOARD_GOOGLE_BASEBOARD_OCTOPUS</span><br><span> select NHLT_DA7219 if INCLUDE_NHLT_BLOBS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_AMPTON</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "-> AMPTON"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BASEBOARD_OCTOPUS_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_OCTOPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_RT5682 if INCLUDE_NHLT_BLOBS</span><br><span>diff --git a/src/mainboard/google/octopus/variants/ampton/Makefile.inc b/src/mainboard/google/octopus/variants/ampton/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..7c092e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/ampton/Makefile.inc</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c7c3eec</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/ampton/gpio.c</span><br><span>@@ -0,0 +1,321 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'</span><br><span style="color: hsl(120, 100%, 40%);">+ * table found in EDS vol 1, but some pins aren't grouped functionally in</span><br><span style="color: hsl(120, 100%, 40%);">+ * the table so those were moved for more logical grouping.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NORTHWEST COMMUNITY GPIOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, UP_20K, DEEP, NF1), /* CX_PREQ_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, UP_20K, DEEP, NF1), /* CX_PRDY_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMC stays active in suspend so disable standby for these pins */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_66, UP_20K), /* LTE_OFF_ODL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_67, UP_20K), /*EN_PP3300_DX_LTE_SOC -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_213, UP_20K), /* TP_AP_GPIO213 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_214, UP_20K), /* P_SENSOR_INT_L -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NORTH COMMUNITY GPIOS */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* svid - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LPSS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_84, NONE), /* LPSS_SPI_2_CLK - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fast SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMU Signals */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2C5 - Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2C6 - Trackpad */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2C7 - Touchscreen */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIE_WAKE[0:3]_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination</span><br><span style="color: hsl(120, 100%, 40%);">+ * guideline for unused PCIE ports as described in PDG i.e. keep</span><br><span style="color: hsl(120, 100%, 40%);">+ * the pins in native mode and deploy the internal pull up.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI[0:1] SDA and SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel 0 control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Hot plug detect. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_134, NONE),/* GPIO_134 -- EC_AP_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1,</span><br><span style="color: hsl(120, 100%, 40%);">+ DISPUPD),/* GPIO_137 -- HP_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ // Also we may be able to use eSPI WAKE# Virtual Wire instead</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_143, UP_20K), /* GPIO_143 - NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_144, UP_20K), /* GPIO_144 - PEN_EJECT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_145, UP_20K), /* GPIO_145 - PEN_EJECT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for</span><br><span style="color: hsl(120, 100%, 40%);">+ * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ * and kept unconnected to allow S0ix entry.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* AUDIO COMMUNITY GPIOS*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_157, DN_20K),/* AVS_I2S0_BCLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_158, DN_20K),/* AVS_I2S0_WS_SYNC -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_159, DN_20K),/* AVS_I2S0_SDI -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_160, DN_20K),/* AVS_I2S0_SDO -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_161, DN_20K),/* AVS_I2S1_MCLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SCC COMMUNITY GPIOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Disable standby state for these CNVI pins to allow wake on</span><br><span style="color: hsl(120, 100%, 40%);">+ * WiFI & Bluetooth.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_210, DN_20K),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_base_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIOs needed prior to ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DISPUPD), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable power to wifi early in bootblock and de-assert PERST#. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak</span><br><span style="color: hsl(120, 100%, 40%);">+ * pull-up for proper operation. Since there is no external pull present</span><br><span style="color: hsl(120, 100%, 40%);">+ * on this platform, configure an internal weak pull-up.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ENPU), /* ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..cc17d56</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/acpi/dptf.asl></span><br><span>diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..16f931b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAINBOARD_EC_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..1fd1e11</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* MAINBOARD_GPIO_H */</span><br><span>diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..cd0ea18</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb</span><br><span>@@ -0,0 +1,55 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/apollolake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/hid</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.hid" = ""WCOM50C1""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.desc" = ""WCOM Digitizer""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "generic.has_power_resource" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid_desc_reg_offset" = "0x1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 0x9 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""10EC5682""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "name" = ""RT58""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Realtek RT5682""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "probed" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "property_count" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set the jd_src to RT5668_JD1 for jack detection</span><br><span style="color: hsl(120, 100%, 40%);">+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "property_list[0].name" = ""realtek,jd-src""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "property_list[0].integer" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 1a on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0000""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchpad""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW2_02"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "probed" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 15 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/generic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = ""ELAN0001""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""ELAN Touchscreen""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "probed" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "reset_delay_ms" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_delay_ms" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_resource" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 10 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # - I2C 7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28663">change 28663</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28663"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 </div>
<div style="display:none"> Gerrit-Change-Number: 28663 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Justin TerAvest <teravest@chromium.org> </div>