<p><a href="https://review.coreboot.org/27619">View Change</a></p><p>13 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h">File src/soc/amd/common/block/include/amdblocks/psp.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@26">Patch Set #13, Line 26:</a> <code style="font-family:monospace,monospace">#define PSP_PCI_MIRRORCTRL1_REG       0x44    /* PSP Mirror Reg Ctrl           */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@27">Patch Set #13, Line 27:</a> <code style="font-family:monospace,monospace">#define PSP_PCI_EXTRAPCIHDR_REG       0x48    /* Extra PCI Header Ctrl         */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@29">Patch Set #13, Line 29:</a> <code style="font-family:monospace,monospace">#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xb8    /* GNB index for SMU mbox        */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@30">Patch Set #13, Line 30:</a> <code style="font-family:monospace,monospace">#define PCI_CONFIG_SMU_INDIRECT_DATA  0xbc    /* GNB data for SMU mbox         */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@32">Patch Set #13, Line 32:</a> <code style="font-family:monospace,monospace">#define PCI_MAGIC_REG1                0xb8    /* PSP Mailbox MMIO control      */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@33">Patch Set #13, Line 33:</a> <code style="font-family:monospace,monospace">#define PCI_MAGIC_REG2                0xbc    /* PSP Mailbox MMIO control      */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@35">Patch Set #13, Line 35:</a> <code style="font-family:monospace,monospace">#define MAGIC_ENABLE_BITS             0x34    /* Extra PCI HDR Ctl Enables     */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@41">Patch Set #13, Line 41:</a> <code style="font-family:monospace,monospace">#define PMNXTPTRW_MASK                0xff    /* PCI ACR MASK                  */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@42">Patch Set #13, Line 42:</a> <code style="font-family:monospace,monospace">#define PMNXTPTRW_EXPOSE              0xa4    /* Control val to expose the ACR */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@46">Patch Set #13, Line 46:</a> <code style="font-family:monospace,monospace">#define SMU_CC_PSP_FUSES_STATUS 0xc0018000ul  /* GNB offset for PSP fusing     */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@50">Patch Set #13, Line 50:</a> <code style="font-family:monospace,monospace">#define PSP_MAILBOX_BASE              0x70    /* Mailbox offset from PCIe BAR  */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@52">Patch Set #13, Line 52:</a> <code style="font-family:monospace,monospace">#define MSR_CU_CBBCFG           0xc00110a2ul  /* PSP Private Blk Base Addr     */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27619/13/src/soc/amd/common/block/include/amdblocks/psp.h@53">Patch Set #13, Line 53:</a> <code style="font-family:monospace,monospace">#define BAR3HIDEBIT                   BIT(12) /* Bit to hide BAR3 addr if set  */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27619">change 27619</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27619"/><meta itemprop="name" content="View Change"/></div></div>

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<div style="display:none"> Gerrit-Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a </div>
<div style="display:none"> Gerrit-Change-Number: 27619 </div>
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<div style="display:none"> Gerrit-Owner: Charles Marslett <charles.marslett@amd.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Charles Marslett <charles.marslett@amd.corp-partner.google.com> </div>
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<div style="display:none"> Gerrit-CC: Marc Jones <marc@marcjonesconsulting.com> </div>
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<div style="display:none"> Gerrit-Comment-Date: Tue, 18 Sep 2018 12:28:36 +0000 </div>
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