<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28662">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/cannonlake_rvp: Move FSP param override function to separate file<br><br>Move the FSP param initialization function to a separate file.<br><br>Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>M src/mainboard/intel/cannonlake_rvp/romstage.c<br>A src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c<br>3 files changed, 54 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/28662/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc</span><br><span>index 7e82196..49d74a6 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc</span><br><span>@@ -22,6 +22,7 @@</span><br><span> verstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span> </span><br><span> romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += romstage_fsp_params.c</span><br><span> </span><br><span> ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span> ramstage-y += mainboard.c</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c</span><br><span>index e0699da..6d9d549 100644</span><br><span>--- a/src/mainboard/intel/cannonlake_rvp/romstage.c</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/romstage.c</span><br><span>@@ -13,42 +13,3 @@</span><br><span> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/byteorder.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cbfs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/api.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/romstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "spd/spd.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spd_bin.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_M_CONFIG *mem_cfg;</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg = &mupd->FspmConfig;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 spd_index;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);</span><br><span style="color: hsl(0, 100%, 40%);">- mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->DqPinsInterleaved = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->ECT = 1; /* Early Command Training Enabled */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_index = 2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- struct region_device spd_rdev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)</span><br><span style="color: hsl(0, 100%, 40%);">- die("spd.bin not found\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Memory leak is ok since we have memory mapped boot media */</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->RefClk = 0; /* Auto Select CLK freq */</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c</span><br><span>new file mode 100644</span><br><span>index 0000000..457be7f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c</span><br><span>@@ -0,0 +1,53 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/byteorder.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbfs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "spd/spd.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <spd_bin.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_memory_init_params(FSPM_UPD *mupd)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_CONFIG *mem_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg = &mupd->FspmConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 spd_index;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->DqPinsInterleaved = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->ECT = 1; /* Early Command Training Enabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ spd_index = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct region_device spd_rdev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("spd.bin not found\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Memory leak is ok since we have memory mapped boot media */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->RefClk = 0; /* Auto Select CLK freq */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28662">change 28662</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa </div>
<div style="display:none"> Gerrit-Change-Number: 28662 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>