<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28633">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/sr5650/sr5650.h: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: Ib4dbb607cfd1e02d45efe141b498d6505574d6e6<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sr5650/sr5650.h<br>1 file changed, 35 insertions(+), 30 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28633/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h</span><br><span>index ea7005c..2e6b728 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.h</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.h</span><br><span>@@ -89,47 +89,52 @@</span><br><span> extern PCIE_CFG AtiPcieCfg;</span><br><span> </span><br><span> /* ----------------- export functions ----------------- */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_p_read_index(device_t dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_p_write_index(device_t dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);</span><br><span style="color: hsl(0, 100%, 40%);">-void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index);</span><br><span style="color: hsl(0, 100%, 40%);">-void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data);</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index);</span><br><span style="color: hsl(0, 100%, 40%);">-void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);</span><br><span style="color: hsl(0, 100%, 40%);">-void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_set_tom(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_p_read_index(struct device *dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_p_write_index(struct device *dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data);</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index);</span><br><span style="color: hsl(120, 100%, 40%);">+void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t data);</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index);</span><br><span style="color: hsl(120, 100%, 40%);">+void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t data);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_set_tom(struct device *nb_dev);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current,</span><br><span style="color: hsl(0, 100%, 40%);">- struct acpi_rsdp *rsdp);</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long current,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct acpi_rsdp *rsdp);</span><br><span> </span><br><span> void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);</span><br><span style="color: hsl(0, 100%, 40%);">-void enable_pcie_bar3(device_t nb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void disable_pcie_bar3(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_pcie_bar3(struct device *nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void disable_pcie_bar3(struct device *nb_dev);</span><br><span> </span><br><span> void enable_sr5650_dev8(void);</span><br><span> void sr5650_htinit(void);</span><br><span> void sr5650_htinit_dect_and_enable_isochronous_link(void);</span><br><span> void sr5650_early_setup(void);</span><br><span> void sr5650_before_pci_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_enable(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void config_gpp_core(device_t nb_dev, device_t sb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);</span><br><span style="color: hsl(0, 100%, 40%);">-void pcie_config_misc_clk(device_t nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_enable(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_gfx_init(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void config_gpp_core(struct device *nb_dev, struct device *sb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void PcieReleasePortTraining(struct device *nb_dev, struct device *dev,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);</span><br><span style="color: hsl(120, 100%, 40%);">+void pcie_config_misc_clk(struct device *nb_dev);</span><br><span> void fam10_optimization(void);</span><br><span> void sr5650_disable_pcie_bridge(void);</span><br><span style="color: hsl(0, 100%, 40%);">-u32 get_vid_did(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void detect_and_enable_iommu(device_t iommu_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_read_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_set_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_iommu_enable_resources(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void sr5650_nb_pci_table(device_t nb_dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void init_gen2(device_t nb_dev, device_t dev, u8 port);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 get_vid_did(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void detect_and_enable_iommu(struct device *iommu_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_read_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_set_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_iommu_enable_resources(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sr5650_nb_pci_table(struct device *nb_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void init_gen2(struct device *nb_dev, struct device *dev, u8 port);</span><br><span> void sr56x0_lock_hwinitreg(void);</span><br><span> struct resource * sr5650_retrieve_cpu_mmio_resource(void);</span><br><span> #endif /* __SR5650_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28633">change 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib4dbb607cfd1e02d45efe141b498d6505574d6e6 </div>
<div style="display:none"> Gerrit-Change-Number: 28633 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>