<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28617">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store<br><br>TODO: test!<br>TODO: clean up<br><br>Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling")<br>Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/arch/riscv/misaligned.c<br>1 file changed, 9 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/28617/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c</span><br><span>index cb045b8..7ac810f 100644</span><br><span>--- a/src/arch/riscv/misaligned.c</span><br><span>+++ b/src/arch/riscv/misaligned.c</span><br><span>@@ -174,11 +174,15 @@</span><br><span> {</span><br><span>  uintptr_t insn = 0;</span><br><span>  union endian_buf buff;</span><br><span style="color: hsl(120, 100%, 40%);">+        bool is_compressed = false;</span><br><span> </span><br><span>      /* try to fetch 16/32 bits instruction */</span><br><span style="color: hsl(0, 100%, 40%);">-       if (fetch_16bit_instruction(tf->epc, &insn))</span><br><span style="color: hsl(0, 100%, 40%);">-             if (fetch_32bit_instruction(tf->epc, &insn))</span><br><span style="color: hsl(120, 100%, 40%);">+   if (fetch_16bit_instruction(tf->epc, &insn) < 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+          if (fetch_32bit_instruction(tf->epc, &insn) < 0)</span><br><span>                   redirect_trap();</span><br><span style="color: hsl(120, 100%, 40%);">+      } else {</span><br><span style="color: hsl(120, 100%, 40%);">+              is_compressed = true;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span>        /* matching instruction */</span><br><span>   struct memory_instruction_info *match = match_instruction(insn);</span><br><span>@@ -264,4 +268,7 @@</span><br><span>                       mprv_write_u8(addr, buff.b[i]);</span><br><span>              }</span><br><span>    }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* return to where we came from */</span><br><span style="color: hsl(120, 100%, 40%);">+    write_csr(mepc, read_csr(mepc) + is_compressed? 2:4);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28617">change 28617</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28617"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 </div>
<div style="display:none"> Gerrit-Change-Number: 28617 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>